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Multi-V DD FPGA Architecture

Multi-V DD FPGA Architecture. CSE 598C Project Fall 2003 Aman Gayasen, Ki-Yong Lee. FPGA overview –Virtex-II architecture. Power Consumption in FPGAs. Orders of magnitude larger than embedded processors (that are being used in mobile devices extensively)

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Multi-V DD FPGA Architecture

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  1. Multi-VDD FPGA Architecture CSE 598C Project Fall 2003 Aman Gayasen, Ki-Yong Lee CSE 598C Project

  2. FPGA overview –Virtex-II architecture CSE 598C Project

  3. Power Consumption in FPGAs • Orders of magnitude larger than embedded processors (that are being used in mobile devices extensively) • No embedded FPGA yet (but on its way) • Static (leakage) power: • Smallest Virtex-II : ~200 mW • No standby modes CSE 598C Project

  4. Dynamic Power Breakdownin Virtex-II Taken from Li Shang et al. FPGA’02 CSE 598C Project

  5. Leakage Power Breakdownof a 90 nm CLB array (Spartan 3) Leakage in Configuration SRAMs can be easily optimized, using conventional techniques • Leakage in Virtex-II FPGA: • ~25% of total power (average) • ~200 mW for smaller Virtex-II devices (0.13 nm) • ~540 mW for largest Virtex-II devices CSE 598C Project

  6. Leakage Recap -Dependence on Vdd • Sub-threshold leakage α Vdd • DIBL α exp(Vdd) • Gate Leakage α exp(Vdd) Lowering Vdd is a good idea to reduce leakage CSE 598C Project

  7. Multi-Vdd Strategy • Let the non-critical paths run at lower voltage • Saves dynamic + static power • Can maintain performance while saving power CSE 598C Project

  8. Issues in multi-Vdd Approach • Optimal voltage assignment is an NP- complete problem. • Level Converters need to be inserted if a low-Vdd gate drives a high-Vdd gate • Consume power. Introduce delay. CSE 598C Project

  9. Multi-Vdd FPGA • Expected to reduce dynamic + static power consumption of logic as well as routing resources. • May need redundant level converters because different designs may need different number/placement of level converters. CSE 598C Project

  10. Versatile Place and Route (VPR) -An FPGA Place and Route tool • Developed at Univ. Toronto • Open source. • Flexible. • Can specify various architectural parameters as inputs • Simple architecture. • Basic CLB design similar to Xilinx/Altera FPGAs CSE 598C Project

  11. VPR – Example architectural parameters • LUT size/inputs • Number of slices (subblocks) in a CLB • Various parameters associated with routing matrix. • Delay values for Timing-Driven Routing • MOS device parameters to estimate power. CSE 598C Project

  12. VPR Power Model • Very powerful tool to study effect of architectural parameters (like number of LUTs in a CLB) on power consumption. • Very basic leakage modeling • (only sub-threshold leakage) • not suitable for 65nm FPGAs • Can’t capture the exponential dependence of gate leakage and DIBL on Vdd. CSE 598C Project

  13. Algorithm used for assigning Vdd’s(for 2 Vdd’s) • List out the paths whose delays become greater than the required clock time period when they are operated at low Vdd. • Assign a criticality attribute to each node in the timing graph. This is a measure of how many paths contain this node. • Generate the (next) longest path • Traverse the nodes in decreasing order of criticality, and mark them as high Vdd till the path delay ≤ Tclock • Repeat 3 and 4 till all paths are covered CSE 598C Project

  14. Algorithm for finding k longest paths from a timing graph • Generate the longest path P1 • Prepare list[1] : ordered list of branch slacks (the branch point that will generate next longest path is at the head of the list) • Calculate next_delay(P1) • While (k paths not enough) • { I = the path with longest next_delay; • J = first branch point in list[1]; • Generate next longest path Pk+1 by branching out from the jth node on path Pi; • Prepare list[k+1] and calculate next_delay(Pk+1); • Update next_delay(Pi); • K = k + 1;} Source: Ju et al. DAC 1991 CSE 598C Project

  15. Results (Average values) CSE 598C Project

  16. Results (Continued) This is only for logic block dynamic power. The effect will be more pronounced when leakage is included in analysis CSE 598C Project

  17. Analysis • Using 1.1V and 0.8V power supplies gives best power savings, while maintaining the performance. • The DIBL and gate leakage will get reduced as exp(VddH – VddL) CSE 598C Project

  18. Circuit Level Work 1. Logic Slice 2. D-flipflop 3. Level Converter 4. Dynamic Power Comparison CSE 598C Project

  19. 65nm, BSIM4 model K-input LUT : Transmission gate mux Edge-Triggered D-Flipflop Logic Slice Design CSE 598C Project

  20. Logic Slice • Combinational Logic Delay : T_comb (psec) Increased by 43% VDD * 0.8V and 1.0V Comparison CSE 598C Project

  21. Logic Slice • Sequential Logic Delay : T_seq_in (psec) Increased by 42% VDD CSE 598C Project

  22. Logic Slice • Sequential Logic Delay : T_seq_out (psec) Increased by 37% VDD CSE 598C Project

  23. Logic Slice • Dynamic Power (uW) • Freq=500MHz Decreased by 47% VDD CSE 598C Project

  24. Logic Slice • Leakage Current (uA) Decreased by 58% VDD CSE 598C Project

  25. D-Flipflop • Dynamic Power (uW) at Freq=500MHz • Compared with 0.18um technology VDD CSE 598C Project

  26. D-Flipflop Comparison • Leakage Current I (pA) I (nA) VDD VDD 180nm, BSIM3 model 65nm, BSIM4 model CSE 598C Project

  27. VDDH Vout VDDL Vin Level Converter • Design • 65nm, BSIM4 model • Delay, Dynamic Power, Leakage Current CSE 598C Project

  28. Level Converter • Vin-Vout Delay (psec) VDDH VDDL * TPHL is shown. CSE 598C Project

  29. Level Converter • Dynamic Power (uW), Freq=500MHz VDDH VDDL CSE 598C Project

  30. Level Converter • Leakage Current (nA) • High voltage transistor substrate voltage = VDDH VDDH VDDL CSE 598C Project

  31. Dynamic Power Comparison • Compare Level Converter and Logic Slice Freq=500MHz • Level converter power consumption is not significant. CSE 598C Project

  32. Summary • We have shown that using 2 voltage supplies is a very effective way to reduce power consumption of FPGAs. • Further, using 1.1V and 0.8V supply voltages gives best power savings, while maintaining the performance. CSE 598C Project

  33. Future Work • Improve power model to get good leakage estimate • Estimate the reduction in routing power due to multi-Vdd . Capture the effect of level conversion. • Extend the algorithm for > 2 Vdd’s • Cluster the sub-blocks running on same Vdd so that independent control of Vdd of each sub-block is not needed. CSE 598C Project

  34. References • K. Poon, A. Yan, and S.J.E. Wilton, “A flexible Power Model for FPGAs”, FPL 2002. • V. Betz and J. Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA Research” FPL 1997 • L.Shang, A.S.Kaviani and K.Bathala, “Dynamic Power Consumption in Virtex-II FPGA Family”, FPGA 2002 • K.Usami and M. Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design”, ISLPD 1995 • P.Pant, V.De, and A.Chatterjee, “Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks”, DAC 1997 • Y-C Ju and R.A.Saleh, “Incremental Techniques for the Identification of Statically Sensitizable Critical Paths”, DAC 1991 CSE 598C Project

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