Enhancing FPGA Architecture with TELL40 MEP Format

NB: slides with power-point animation First thought on the TELL40 FPGA architecture Consult some studies from Guido Haefeli, Lausanne from Jean-Pierre Cachemiche, Marseille from Xavier Gremaud, Lausanne from Renaud Le Gac, Marseille Extract some concepts 1st March 2012 7 cyril.drancourt@lapp.in2p3.fr

Hight LevelProcessing USER Event buildingand processing COMMON MEP building Low LevelInterface 10 GbE GBT x-FPGA Ck + throttle PCI-express Tests DDR3 DCB (1) from Jean-Pierre, 13oct2011 from Renaud, 23janv2012 7 cyril.drancourt@lapp.in2p3.fr

from Guido, 13oct2011 7 cyril.drancourt@lapp.in2p3.fr

from Xavier, 10fev2011 7 cyril.drancourt@lapp.in2p3.fr

SUMMARY 7 cyril.drancourt@lapp.in2p3.fr

MEP Format • It is not clear to me that MEP builder is a common firmware module. • Is it necessary to create a new format for 40 MHz flow or can we keep the current format? • I think we need a specific meeting with Online team and TELL40 users about MEP format. 7 cyril.drancourt@lapp.in2p3.fr

from Renaud, 23janv2012 ? Wedon’t know yet if we’ll have necessary ressources at LAPP 1st March 2012 7 cyril.drancourt@lapp.in2p3.fr

Enhancing FPGA Architecture with TELL40 MEP Format

Enhancing FPGA Architecture with TELL40 MEP Format

Presentation Transcript

Ethernet on the FPGA

Network-on-FPGA

ETRAX CRIS architecture and Xilinx FPGA

Compact Architecture for High-Throughput Regular Expression Matching on FPGA

FRC FPGA Architecture

FPGA Architecture, timing, Software

FPGA Architecture, timing, Software

FPGA Global Routing Architecture

TELL40 Data processing

Octavo: An FPGA-Centric Processor Architecture

VELO Upgrade Tell40.

Multi-V DD FPGA Architecture

FPGA Design, Symmetrical Architecture Approach

Xilinx FPGA Architecture

TELL40 Data processing

High-performance Architecture for Dynamically Updatable Packet Classification on FPGA

Network-on-FPGA

FPGA Architecture

First thought…

First thought…

Basic FPGA Architecture

FPGA Architecture