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EECS 465: Digital Systems

EECS 465: Digital Systems. Lecture Notes # 8. Sequential Circuit (Finite-State Machine) Design. SHANTANU DUTT. Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) 355-1314: e-mail: dutt@eecs.uic.edu URL: http://www.eecs.uic.edu/~dutt.

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EECS 465: Digital Systems

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  1. EECS 465: Digital Systems Lecture Notes # 8 Sequential Circuit (Finite-State Machine) Design SHANTANU DUTT Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) 355-1314: e-mail: dutt@eecs.uic.edu URL: http://www.eecs.uic.edu/~dutt

  2. Finite State Machine (FSM) Design Sampling instances x O/p y Tlogic + Tsetup FSM CLK CLK x # of 1s even (0) odd (1) even (2) odd (3) odd (3) • • FSMs are different from counters in the sense that they have external I/Ps, and state transitions are dependent on these I/Ps and the current state. • • Example : Problem Statement • There is a bit-serial I/P line. Design an FSM that outputs a ‘0’ • if an even # of 1’s have been received on the I/P line and the • outputs a ‘1’ otherwise. • When do we need an FSM (i.e., seq ckt) to solve a problem rather than a combinational ckt? • Ans: When the problem requires the design to remember something about past inputs in order to solve the problem • Note : If a +ve edge triggerred synchronous sequential circuit is being designed, • the counting of the # of 1s (i.e., the sampling of the input(s), • for a general FSM) occurs Tlogic +Tsetup time before every +ve edge.

  3. Approach to determining states of an FSM: • First determine the min # of useful information classes about past i/ps required to solve the problem (requires analytical thinking about the problem) • Each info class  a potential state • From this 1st cut at possible states, determine if there are well-defined transitions from each state for all possible i/p values. • If so then these states can be the final states; otherwise some states may need to be refined into multiple states to achieve well-defined transitions (see FSM word prob. 1). • • In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states. Solution 2: (Moore) 0 Solution 1: (Mealy) 0/0 Reset Even Reset Output [0] Even Input 1 1 1/1 O/P is dependent on current state and input in Mealy 1/0 Input Odd [1] Output Output is dependent only on current state Odd Transition Arc 0 0/1 Moore Machine: Output is associated with the state and hence appears after the state transition take place. Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse).

  4. Determining a Reset State: • A reset state is a state the the FSM (seq ckt) should be in when it is just powered on. • In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps • Based on the above definition, decide if any of the states determined so far can be a reset state. E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd  zero 1’s recvd  even # of 1’s recvd  it can be the even state • If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM). Solution 1: (Mealy) Solution 2: (Moore) 0 0/0 Reset Reset Even Even Input Output [0] 1/1 O/P is dependent on current state and input in Mealy 1/0 1 1 Input Output Odd Odd [1] Transition Arc Output is dependent only on current state 0 0/1 Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse). Moore Machine: Output is associated with the state and hence appears after the state transition take place.

  5. External I/Ps Next State Comb. Logic External I/Ps External O/Ps m1 m1 Comb. Logic m2 FFs n n FFs Output Logic n n CLK External Outputs m2 CLK even  odd Moore Machine Model Mealy Machine Model Time t : Even I/P  = propagation delay of logic of Mealy M/C 2 = propagation delay of O/P logic unit of Moore M/C t+TCLK+2 t+ t+TCLK t Even x=1 O/P=0 Odd O/P=1 (Moore) O/P=1 (Mealy)

  6. State Transition Table (Even-Parity Checker) Even State: 0 ; Odd State: 1; State Variable A Next State Present State Mealy O/P D-FF Excit. Moore O/P T-FF Excit. Input A x A+ y1 y2 DA TA 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 1 0 0 1 Output functions Input variables to comb. logic y2 x x N.S. Logic N.S. & O/P Logic Or DA= Ax ; TA= x y1 = A for Moore y2 = Ax for Mealy Q FF Q FFs DA A DA A O/P Logic y1 CLK

  7. Reset 0 0/0 State=0 Even Reset State=0 Even [0] 1/1 1/0 1 1 State=1 Odd N.S. Logic x State=1 Odd [1] Q 0/1 0 D- FF Q D Mealy Moore CLK S.T. is complete. Assume single bit state information stored in a D-FF State Transition is occurring State Transition is occurring S.T. is complete. CLK x D even even even odd Q (state) odd odd y2 (Mealy O/P) y1 Moore O/P)

  8. Reset Reset Reset Reset DA= Ax ; TA= x y1 = A for Moore; y2 = Ax for Mealy Moore M/C Implementation a) D-FF b) T-FF 0 x A y2 A y1 T Q D Q x=1 CLK Q R Q R CLK Moore O/P is synchronized with clock. Mealy M/C Implementation y2 x y1 0 T Q 1 A D Q x=1 CLK Q R Q R CLK b) T-FF a) D-FF Mealy O/P is not synchronized with clock.

  9. Difference Between Mealy and Moore Machine Mealy Moore (1) O/Ps depend on the present O/Ps depend only on the state and present I/Ps present state (2) The O/P changes asyn Since the O/Ps change -chronously with the when the state changes, enabling clock edge and the state change is synchronous with the enabling clock edge, O/Ps change synchronously with this clock edge (3) A counter is not a Mealy A counter is a Moore machine machine (4) A Mealy machine will have the same # or fewer states than a Moore machine

  10. Another example: A simple vending machine Here is how the control is supposed to work. The vending machine delivers a package of gum after it has received 15 cents in coins. The machine has a single coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor indicates to the control whether a dime or a nickel has been inserted into the coin slot. The controller’s output causes a single package of gum to be released down a chute to the customer. One further specification: We will design our machine so it does not give change. A customer who pays with two dimes is out 5 cents! Coin Sensor Gum Release Mechanism Vending Machine FSM Open Reset CLK Vending Machine block diagram States: 0C 5C 10C 15C

  11. Reset / 1 Reset — The figure below show the Moore and Mealy machine state transition diagrams. Reset / 0 )/0 Reset Reset )/0 Reset 0 cent 0 cent [0] Reset / 0 Reset N / 0 N D / 0 5 cent 5 cent [0] D D/1 N N / 0 D 10 cent 10 cent [0] N+D N+D/1 >=15 cent [1] >=15 cent Moore machine Mealy machine Moore and Mealy machine state diagrams for the vending machine FSM

  12. —State transition table for Moore and Mealy M/C.(Next state also gives D-FF excitation). Present State Inputs Next State Moore Output Mealy Output Q1 Q0 D N Q1+ Q0+ Open Open 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 x x x x 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 1 0 1 1 1 x x x x 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 x x x x 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 x x x x Q+ = D Q Q+ D 0 0 0 0 1 1 1 0 0 1 1 1 Encoded vending machine state transition table.

  13. Q1Q0 Q1Q0 Q1Q0 Q1Q0 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 DN DN DN DN 00 00 00 00 01 01 01 01 11 11 11 11 10 10 10 10 Implementation using D-FFs 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 0 x x x x x x x x x x x x 1 1 1 1 0 1 1 1 0 0 1 0 K-map for Open (Moore) K-map for D1 K-map for D0 D1 = Q1 + D + Q0·N 0 0 1 0 0 0 1 1 OPEN = Q1·Q0 OPEN = Q1·Q0 + D·Q0 + D·Q1 + N·Q1 Moore x x x x Mealy 0 1 1 1 K-map for Open (Mealy)

  14. Reset Reset Q1 D1 Q1 D D Q Q0 Similarly, a Mealy implementation; only the OPEN function changes. CLK Q R N OPEN N Q0 D0 Q0 D Q CLK Q1 Q R N Q1 D Vending machine FSM implementation based on D flip-flops(Moore).

  15. Implementation using J-K FFS J-K Excitation Q1 Q0 D N Q1+ Q0+ J1 K1 J0 K0 0 0 0 0 0 0 0 x 0 x 0 1 0 1 0 x 1 x 1 0 1 0 1 x 0 x 1 1 x x x x x x 0 1 0 0 0 1 0 x x 0 0 1 1 0 1 x x 1 1 0 1 1 1 x x 0 1 1 x x x x x x 1 0 0 0 1 0 x 0 0 x 0 1 1 1 x 0 1 x 1 0 1 1 x 0 1 x 1 1 x x x x x x 1 1 0 0 1 1 x 0 x 0 0 1 1 1 x 0 x 0 1 0 1 1 x 0 x 0 1 1 x x x x x x Q Q+ J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0 Remapped next-state functions for the vending machine example.

  16. Q1Q0 Q1Q0 Q1Q0 Q1Q0 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 DN DN DN DN 00 00 00 00 01 01 01 01 11 11 11 11 10 10 10 10 0 0 x x x x 0 0 0 1 x x x x 0 0 x x x x x x x x 1 1 x x x x 0 0 K-map for J1 K-map for K1 0 x x 0 x 0 0 x 1 x x 1 x 1 0 x x x x x x x x x 0 x x 1 x 0 0 x K-map for J0 K-map for K0 K-maps for J-K flip-flop implementation of vending machine. J1 = D + Q0·N K1 = 0

  17. Reset N Q0 Q1 J Q CLK D Q R K OPEN N Q1 Q0 D J Q CLK Q R K N J-K flip-flop implementation for the vending machine example (Moore). Similarly, a Mealy implementation; only the OPEN function changes.

  18. Basic Steps in the FSM Design Procedure • 1. Understand the problem and determine the minimal # of different information classes about past i/ps required to solve it. • 2. Convert these information classes into distinct states (which we informally call tentative states), and determine the state transition diagram of the FSM. • 3. If the state transitions between states are well-defined (i.e., for each state and i/p value, it is unambiguous what the next state should be), then these are the final states. • Otherwise, states from which transitions are not well defined need to be broken into multiple states (called extra states) so that • non-well-defined transitions are then translated to well-defined transitions between the original state(s) that did not have all transitions well-defined, and the extra state(s), and also from the extra state(s) to other original states (see, e.g., FSM prob. 1 next) • 4. Determine the reset state • 5. Perform state minimization • 6. Encode states in binary [optional—perform state assignment for logic minimization], and obtain state transition table and FF • excitation for desired FF type. • 7. Minimize the FF input functions (using K-Maps or QM, for example) and implement the FSM using these FFs and logic gates (or MUXes, PLAs, PALs, etc.) that implement the FF’s input functions.

  19. FSM Word Problem 1: • Design a system that outputs a ‘1’ whenever it receives a multiple of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x. — Relevant information classes needed to solve the problem: (A) A multiple of 3 # is received. (B) A non-multiple of 3 # is received. Questions to consider: (1) How do we go from (A)(B) Ans.: If a ‘1’ is received (2) How do we go from (B)(A) Ans.: Not clear. Need to split up (B) further into (B1): 3y+1 # of 1’s received. (B2): 3y+2 # of 1’s received. Where y is an integer  0.

  20. Note: (A): is 3y+0 = 3y # of 1’s received. • Now the transitions between the3 classes of information is clear: (A)  (B1)  (B2)  (A) 1 received 1 received 1 received • Hence these classes of information can be considered states of the required as states of the required FSM: These 3 states can be represented by 3y+I, i = 0,1,2 0 Output 00 0/1 Reset Reset i=0 i=0 [1] Input 0/0 1 0 1/0 i=1 1/1 01 1 i=1 [0] i=2 1/0 i=2 [0] 10 1 0/0 0 Mealy Machine Moore Machine

  21. FSM Word Problem 2: • Design a system that outputs a ‘1’ whenever it receives: (a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s E.g., ((0,2) , (3,2) , (3,4) , (6,2) ,···) — Relevant classes of information: Use D&C to figure this out! - Break problem into relevant classes of # of 1’s & relevant classes of # of 0’s - For # of 1’s: 3y+i, i = 0,1,2 [3 classes] - For # of 0’s: 2z+j, j = 0,1 For j = 0, we need to distinguish between zero (z = 0) and non-zero (z > 0) # of 0’s - Thus we have 3 classes: 2z+0, z = 0 ( 0 ) 2z+0, z > 0 ( non-zero even ) 2z+1 ( odd ) # of 1’s # of 0’s

  22. The relevant # of 1’s can be represented by i = { 0, 1, 2 } ( # of 1’s = 3y+i ) — The relevant # of 0’s can be represented by j= { 00 , 0>0 , 1 } ( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether z=0 or z>0. — Since at any point time, a certain # of 1’s and # of 0’s will have been received, the state of the system will be given by a combination of relevant # of 1’s and # of 0’s. — There are 9 combinations: { 0, 1, 2, } X { 00, 0>0, 1 } = (0,00), (0,0>0), (0,1), (1,00), (1,0>0), (1,1), (2,00), (2,0>0), (2,1)  # of 1’s # of 0’s Cartesian Product

  23. (0,00) (0,0>0) (1,00) (0,1) (2,00) (1,1) (2,1) (1,0>0) (2,0>0)

  24. Note: 0>0 2z+j, j = 0 z > 0 Reset (0,00) 0/0 1/0 1/0 (0,0>0) (1,00) 0/0 1/0 0/0 0/1 1/0 (0,1) (2,00) (1,1) 1/0 0/0 0/0 1/0 0/0 (2,1) (1,0>0) 1/1 0/0 1/0 0/0 (2,0>0) 1/0

  25. 0 0 i=0 [1] j=0 z=0 [0] 1 1 0 0 x 1 1 j=1 [0] i=1 [0] j=0 z>0 [1] i=2 [0] FSM2 FSM1 1 1 o/p1 o/p2 AND y • Another option is to have 2 independent FSM’s one for detecting the desired # of 1’s and another for the desired # of 0’s. The o/p of the combined machine is 1 when both FSM’s are in states w/ o/p = 1 Interacting FSMs For # of 0’s: 2z+j, j = 0,1 For j = 0, we need to distinguish between zero (z = 0) & non-zero (z > 0) # of 0’s [3 classes]: FSM2 For # of 1’s: 3y+i, i = 0,1,2 [3 classes]: FSM1 Reset Reset • Each pair of states of the 2 FSMs  a state of the composite fsm (previous design) 1 state pair • Do we save on FFs here? • What about the general case (in • which we divide an FSM w/ m1*m2 states into 2 FSMs, one w/ m1 and the 2nd w/ m2 states ? • Do we save on logic (here and in general)?

  26. 0 1 i=0 [1] j=0 z=0 [0] 1 0 0 1 x 1 j=1 [0] i=1 [0] i=2 [0] j=0 z>0 [1] FSM2 FSM1 0 1 o/p1 o/p2 1 AND y Interacting FSMs (contd) Reset Reset • Each pair of states of the 2 FSMs  a state of the composite fsm (previous design) 0 a state pair • Q: When can a single FSM design be broken into 2 or more interacting fsm’s? • A: When the compound o/p-change condition can be broken up into multiple smaller o/p change conditions joined together by some logical opreations (as in this example). In such a case, these smaller conditions can each be determined by a simpler fsm. Each of these simpler fsm’s o/ps are used to determine the final o/p (via external logic depending on how the multiple conditions logically form the original compound condition).

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