I.N.P Trigger Group T. Geralis S. Kyriazopoulou C. Markou K. Zachariadou

1. The Global Trigger Processor Emulator System (eGTP) for the CMS experiment Dr. Katerina Zachariadou I.N.P Trigger Group T. Geralis S. Kyriazopoulou C. Markou K. Zachariadou ---------------------------------------------------- I. Michailakis (Electronics Engineer) IEEE-NSS Rome 2004

2. Dr. Katerina Zachariadou Outline • Introduction CMS - DAQ system • The eGTP system in the CMS-DAQ • Hardware and Configuration • Design • Hardware interfaces • Performance Tests IEEE-NSS Rome 2004

3. 3D view of the CMS - DAQ system IEEE-NSS Rome 2004

4. The Level 1 Accept (L1A) signal is sent via the Timing, Trigger and Control (TTC) optical network to all the Front-End Drivers (FED) of the sub-detectors and to the Event Manager (EVM). FES TTC FED EVM (*8) The GTP system in the CMS-DAQ RTP TPG LV1 sTTS aTTS FRL GTP RCN RU FRL BCN BDN FED Builder GTP controls the delivery of L1A signals according to feedback signals through the Trigger Throttling System (TTS). BU IEEE-NSS Rome 2004

5. RTP TPG FES LV1 TTC FED sTTS aTTS FRL eGTP LV1A (*8) RCN RU FRL BCN BDN FED Builder BU EVM (*8) The eGTP in the CMS-DAQ • testing the performance of the DAQ components during development (Preseries) • testing the performance of the DAQ system in run conditions. (The eGTP will be part of the final system running in parallel with the GTP system) • during the DAQ system installation, the eGTP will be used to decouple the LV1 system from the readout system IEEE-NSS Rome 2004

6. Front D E A Data are transferred into a second GIII card (receiver)via the SLINK-64 protocol and are retrieved by a readout software. eGTPboard Data Receiver board SLINK-64 B C F The GIII-board Rear The eGTP is based on a generic, PCI 64bit/66 MHz board (GIII) . • FPGA (APEX –Altera400K) • 32 MB SDRAM (133Mhz) • C. 1 MB Flash • D. Slink-64 connectors (data transmission) • E. User connectors • F. PCI interface for 32b/64b @33/66MHz GIII is plugged into a PC (Linux), eGTP is controlled via dedicated user’s interface processes) IEEE-NSS Rome 2004

7. Quartus 2.2 -Altera DK1 1.1 Celoxica PCI control Counters GTP emulation 8 JTAG SLINK-64 control The eGTP system General FPGA Configuration IEEE-NSS Rome 2004

8. To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd Set from PCI GTP Control 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI 1. Emulation of the LHC proton beam structure Free space Data_to_slink Event counters Data[64:0] GTP fragment data The eGTP system Functional block diagram -Tasks IEEE-NSS Rome 2004

9. The eGTP system Functional block diagram To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd Set from PCI GTP Control 2.partitioning (eight DAQ partitions - eight sub-detector parts in each DAQ partition). The partition selection is set from the PCI 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI Free space Data_to_slink Event counters Data[64:0] GTP fragment data IEEE-NSS Rome 2004

10. To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd Set from PCI GTP Control 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI Free space Data_to_slink Event counters Data[64:0] 3.random generationof Level-1accept triggers for each partition. (only at non-empty BX and at any frequency defined by the user (10Hz to 123 kHz) The associated rates for each partition are set from the PCI GTP fragment data The eGTP system Functional block diagram -Tasks IEEE-NSS Rome 2004

11. The eGTP system Functional block diagram To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 4. generation of trigger summary data formatted as seven 65-bit words (d0-d6) to be sent to the FED Builder-Event Manager. d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd Set from PCI GTP Control 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI Free space Data_to_slink Event counters Data[64:0] GTP fragment data IEEE-NSS Rome 2004

12. To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd 5. receipt of feedback signals from DAQ partitions & sub-detector parts +.. interpreted as inhibit of all Level-1 triggers Set from PCI GTP Control 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI Free space Data_to_slink Event counters Data[64:0] GTP fragment data The eGTP system Functional block diagram IEEE-NSS Rome 2004

13. To FRL trigger distribution system LV1All 8 8 BX Clk40M LV1A Clk40M BX_gen GTP_cmd d0 WR_buf aTTS_Busy d1 Write_evm (cyclic buffer) sTTS_Busy 8 d2 L1_ Gen (LFF) EVM_BUSY d3 SetRate_Partition_0 65 d4 SetRate_Partition_1 d5 . . SetRate_Partition_7 d6 22 65 GTP_cmd GTP_cmd Set from PCI GTP Control 8 WR_buf 8 8 Local FIFO 65x128 Read_from_PCI Free space Data_to_slink Write_evm receives data fragments in parallel. Data flow out to the receiver via S-LINK64 Event counters Data[64:0] GTP fragment data The eGTP system Functional block diagram IEEE-NSS Rome 2004

14. Interfaces to Trigger Distribution System & Throttling System receives 4 LVDS signals from each of 8 sub-detector partition controllers (ready, busy, warning,out_of_sync). If a sub-detector sends a NOT READY signal the eGTP inhibits L1A for the partition in which the sub-detector belongs. 8 x aTTS aTTS eGTP-IO encoder/ decoder RJ45/LVDS FRL TTS 8 x sTTS 8 x aTTS Lemo/ TTL FRL partitions 8 x sTTS 8xL1A eGTP GIII 8xL1A SLINK-64 receives 4 LVDS signals from each of the 8 aTTS DAQ partition controllers. • Sends its status FRL FED (EVM) switch x8 distributes 8 L1A signals to the sub-detector partitions The eGTP sends the L1A data fragments to the FED Builder EVM Hardware Interfaces to external systems Interface to EVM IEEE-NSS Rome 2004

15. S-LINK64 cable from eGTP to eGTP L1A aTTS/ sTTS/status eGTP-IO EVM receiver eGTP IEEE-NSS Rome 2004

16. eGTP-IO CMC S-LINK64 CMC eGTP GIII board IEEE-NSS Rome 2004

17. eGTP test-bench EVM receiver GIII SLINK to the scope GTP emulator IEEE-NSS Rome 2004

18. The eGTP system’s user interface Global Reset STOP/GetReady StartRun Partition rate selection 10Hz – 123kHz Muon DT Muons RPC Muons CSC HCAL ECAL Presh. Tracker Pixel Sub-detector parts selection IEEE-NSS Rome 2004

19. and that the LHC beam structure is correctly reproduced Performance Tests verify that the system responds adequately to the S-LINK64 backpressure IEEE-NSS Rome 2004

20. Event generation according to Poisson Statistics (for events generated at 120kHz) Performance Tests-cont. • Trigger number, partition event number and trigger rules have been verified for a large number of accumulated events (up to 2x109) for trigger rates 10kHz up to 123kHz and for different DAQ partition and sub-detectors partition schemes (up to 8 partitions). Totally ~800kHz ~50MB/s • The event timing has been tested, for different trigger rates, to follow Poisson statistics IEEE-NSS Rome 2004

21. Summary A Global Trigger Processor Emulator (eGTP) System has been developed at I.N.P Demokritos-Greece The eGTP System tasks : L1A triggers generation, partitioning, emulation of the LHC proton beam structure, generation of trigger summary pseudo-data, receipt of feedback signals Extensive tests have verified the succesful system’s performance Final version of the eGTP system has been delivered at CMS IEEE-NSS Rome 2004