PowerPoint Overheads for Computer Architecture From Microprocessors To Supercomputers

1. PowerPoint Overheads for Computer ArchitectureFrom Microprocessors To Supercomputers Behrooz Parhami

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4. 1.1 Signals, Logic Operator, and Gates Figure 1.1 Some basic elements of digital logic circuits, with operator signs used in this book highlighted.

5. Figure 1.2 Gates with more than two inputs and/or with inverted signals at input or output.

6. Figure 1.3 An AND gate and a tristate buffer can act as controlled switches or valves. An inverting buffer is logically the same as a NOT gate.

7. Figure 1.4 Wired OR allows tying together of several controlled signals.

8. Figure 1.5 Arrays of logic gates represented by a single gate symbol.

9. Truth table N-variable input: 2n x: don’t care. x in output column means no interest; x in input column means that function does not depend on the value of the particular variable involved. Logic expression NOT takes precedence over AND AND takes precedence over OR/XOR Logic expression can be manipulated using laws of Boolean algebra in order to obtain an equivalent logic expression for simpler or more suitable hardware realization. Word statement Natural language Logic diagram Graphical representation of a Boolean function that carries information about its hardware realization. Logic circuit synthesis: derive logic diagram from truth table, logic expression, or word statement. Logic circuit analysis: going backward from logic diagram to truth table, logic expression, or word statement. 1.2 Boolean Functions and Expressions

10. Table 1.1 Three 7-variable Boolean functions specified in a compact truth table with don’t-care entries in both input and output columns.

11. Table 1.2 Laws (basic identities) of Boolean algebra.

12. 1.3 Designing Gate Networks Figure 1.6 A two-level AND-OR circuit and two equivalent circuits.

13. BCD to 7-segment decoder Figure 1.7 Seven-segment display of decimal digits. The three open segments may be optionally used. The digit 1 can be displayed intwo ways, with the more common right-side version shown.

15. Figure 1.8 The logic circuit that generates the enable signal for the lowermost segment (number 3) in a seven-segment display unit.

16. Multiplexer 2a input signals: x0, x0, …,xN (N=2a-1) Single output z a control signal (address signal): y0, …, ya-1 Decoder a input signals 2a output signals Assert one and only one of its 2a output lines Encoder: opposite of a decoder. 2a input signals a output signals When one and only one of its 2a input lines is asserted, its a-bit output supplies the index of the asserted input in the form of a binary number 1.4 Useful Combinational Parts

17. Multiplexer Figure 1.9 A multiplexer (mux), or selector, allows one of several inputs to be selected and routed to output depending on the binary value of a set of selection or address signals provided to it.

18. Decoder Figure 1.10 A decoder allows the selection of one of 2aoptions using an a-bit address as input. A demultiplexer (demux) is a decoder that only selects an output if its enable signal is asserted.

19. Encoder Figure 1.11 A 2a-to-a encoder outputs an a-bit binary number equal to the index of the single 1 among its 2ainputs.

20. Programmable Combinational Parts Figure 1.12 Programmable connections and their use in a PROM.

21. Figure 1.13 Programmable combinational logic: general structure and two classes known as PAL and PLA devices. Not shown is PROM with fixed AND array (a decoder) and programmable OR array.

22. PLD: Short for programmable logic device, a generic term for an integrated circuit that can be programmed in a laboratory to perform complex functions.(i) PROMs (Programmable Read Only Memory) - offer high speed and low cost for relatively small designs (ii) PLAs (Programmable Logic Array) - offer flexible features for more complex designs (iii) PAL/GALs (Programmable Array Logic/Generic Array Logic) - offer good flexibility and are faster and less expensive than PLAs

23. Example: f = x + y + z, using circuit in Fig.13b Figure 1.14 Timing diagram for a circuit that exhibits glitching.

24. CMOS:Complementary metal–oxide–semiconductor

25. The CMOS transmission gate s s s s P A (Vin ) B (Vout ) N s A (Vin ) B (Vout ) C s MOS Circuit TG Symbol The conduction path through TG is controlled by complementary signals & s A B=A (or Z when S=0) In steady state s • A(Vin) S Tn Tp B (Vout) • 0 0 off off Z (high impedance state (blocks logic flow)) • 0 1 on off 0 (nMOS passes strong 0, pMOS off when Vout<Vthp) • 1 0 off off Z (high impedance state (blocks logic flow)) • 1 1 off on 1 (pMOS passes strong 1, nMOS off when Vout>Vdd-Vthn )