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All-Digital TAD-OFDM Detection for Sensor Interface Using TAD-Digital Synchronous Detection. Takamoto Watanabe and Tomohito Terasawa Corporate R&D Dept. 3 DENSO CORPORATION Kariya, Aichi 448-8661, JAPAN. ICECS 2010 December 14 Athens, Greece. Outline. Introduction Operation principle
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All-Digital TAD-OFDM Detection for Sensor Interface Using TAD-Digital Synchronous Detection Takamoto Watanabe and Tomohito Terasawa Corporate R&D Dept. 3 DENSO CORPORATION Kariya, Aichi 448-8661, JAPAN ICECS 2010 December 14 Athens, Greece
Outline • Introduction • Operation principle • Circuit structure and filter effect • TAD-synchronous detection • TAD-OFDM detection • Evaluation results • Conclusions
Digital sensor IC Element Sensor circuit Digital data Electrical Physical DSP AD 0–10 mV 0–100 ns Introduction – Research Background – What is the ideal ADC? All-digital ADC TAD Very high resolution Conventional ADCs can not do the job! All-digital circuit construction Very compact Very low power consumption Very high speed
Key concept - ADC core circuit must be fully digital circuit. - Every correction and compensation must be achieved by digital signal processing after ADC. TAD solution
Domino Toppling P1 P8 P2 P7 Operation principle of TAD* Pulse delay line *TAD: Time A/D converter Vin Delay unit (2 inverters) (DU = Domino) Start pulse Td (Delay time) P7 P8 P1 P2 Delay pulses Ts (fixed time interval) time Delay pulses = Domino effect Toppling speed is modulated by Vin Ts DT = 7
(Impedance converter) Ring-Delay-Line: RDL Vin (25 = 32 inverters) DU DU: Delay Unit Vin 18-bit Counter Start P In Out P16 P1 P2 Ts CKs Latch & Encoder Latch 18-bit 4-bit [Equation (1)] DTp 1 fs (Vin – Vth)a AVin Latch DT= + fs: sampling frequency A and a: constant (Ts= 1/fs) + 22-bit DT Block diagram of TAD core All-digital construction
RDL TAD core photomicrograph Ring delay line: RDL All digital circuits Compact & scalable Ideal means to ease both IC-design and IC-testing Photo of 22-bit TAD-IC chip 0.85 mm × 0.40 mm (0.65-m CMOS)
DT DT 15 k 1,500k 10 k 1,000k 5 k 500k 0 0 1.5 2.0 2.5 1.5 2.0 2.5 Vin (V) Vin (V) A/D conversion characteristics (Vin range 1.3–2.6 V, at 25℃ in 0.65-m CMOS) (a) Sampling frequency fs = 1 kHz (Ts = 1 ms) (b) Sampling frequency fs = 100 kHz (Ts = 10 ms) Input voltage span 1000 mV (1.5 - 2.5 V) 1.06 mV/LSB (fs = 1 kHz) 106 mV/LSB (fs = 100 kHz) Resolution (Vd) Non-linearity 1% FS (see digital-correction methods) A desirable resolution for applications can be used just by selecting a sampling rate
TAD filter effect No sample hold 【Principle of TAD operation】 RDL Averaging delay time of each DU Vin DU Moving average Start P Delay pulse [1] [2] Td Analog Integration circuit (LPF) Dominoes Ts (= Sampling period) Case 1: No noise Ts [1] [5] [2] [6] [10] Vin = 2.0 V (constant) Equal Toppling speed: constant Case 2: Noise exists Fast [1] [2] [5] [6] [10] Vin = 2.0 V x mV Toppling speed: varying Slow
= (dB) 1 k 10 k 100 k 1 M f (Hz) (: Sampling period Ts) t Evaluation results for TAD filter : Experimental results Theory of moving average of continuous signal (Analog moving average) Notch area = Sampling frequency fs = 100 kHz Amplitude [Equation (2)] = Sampling period t = 10 s Pre-filter is unnecessary TAD filter effect = Moving average Clock noise is removed
DT DT 10 mV/div 5 ms/div [1] ×10 (ms) DT2 ×10 (ms) [2] Magnet Pick-up coil Digital filter ×10 (ms) TAD 10 Vin DT DT2 DT2 ~30 Hz CMOS- Amp CKs (100 kHz) Driving coil (Average of 16 data) 2 ×10 (ms) Magnet position sensing 120 mV/LSB Vin (c) Area [1] (b) (a) (d) Sensor block diagram (e) Area [2]
Volt Carrier wave (fc) [d] Bias level [c] [a] [b] 0 time Ts CKs (fs = 2 x fc) [b] [a] DT TAD-digital synchronous detection TAD-DSD DS = [a] – [b] = [c] + [d] Carrier amplitude
[d] Car-A [c] [a] SWA (fA ) [b] time SWB (2fA ) [j] SWC (4fA ) Car-B SWD (8fA ) [i] [e] [g] time time [f] [h] (Car-A + Car-B) Composite waveform (CWA-D) [k] [l] [m] time [n] Ts time CKs TAD-OFDM detection method ■ Carrier (SWA-D) frequency: fA = 1.6 MHz, fB = 3.2 MHz fC = 6.4 MHz, fD = 12.8 MHz ■ TAD-OFDM frequency: fs = 25.6 MHz (a) (b) DS-1 = ([k] + [l]) – ([m] + [n]) = [c] + [d] Car-A amplitude DS-2 = ([k] + [m]) – ([l] + [n]) = 2 x ([i] + [j]) Car-B amplitude
40 40 Aam 30 30 20 20 Bam–Dam Bam–Dam Detection level (LSB) Detection level (LSB) 10 10 Aam 0 0 -10 -10 0 400 800 0 400 800 Sampling counts Sampling counts Experimental results (a) VA = 100 mVp-p, and VB-D = 0 V (b) VA = 0 V, and VB-D = 100 mVp-p All-digital TAD-OFDM with high accuracy
Electrode z-axis y-axis x-axis Mass Electrode Application example Multi-axis accelerometers/angular-rate sensors with force-balance technology (servo-sensing system) TAD-OFDM detection Car-B/electrostatic force Composite signal out Single MEMS element Car-A/electrostatic force Car-A/electrostatic force Car-B/electrostatic force Keeping the MEMS element in the null position
Conclusions 1. Original A/D system (TAD) using a completely digital circuit has been developed. 2. Magnet position sensing with TAD filter and digital post- processing was experimentally confirmed. 3. TAD-digital synchronous detection TAD-DSD with all- digital circuits was proposed. 4. TAD-OFDM detection method with TAD-DSD using four square-wave carriers was experimentally confirmed. 5. An all-digital multi-carrier detection for MEMS sensor systems was introduced.
Conversion data DT Conversion data DT Measured data Measured data Vr1 Vr3 Vr2 Vr1 Vr3 Vr2 Input voltageVin Input voltageVin Vin center voltage (V) Vin span 1.8 2.0 2.5 200 mV ±0.130 ±0.207 ±0.182 Non-correction 1000 mV - - ±1.022 Multi-line Approxi- mation 200 mV ±0.037 ±0.047 ±0.052 1000 mV - - ±0.264 Parabolic Approxi- mation 200 mV ±0.011 ±0.005 ±0.001 1000 mV - - ±0.041 Non-linearity digital-correction method [Equation (2)] Multi-line approximation Parabolic approximation Example of non-linearity error with correction Digital correction process will be very effective (%FS)
1,327,300 1,326,800 548 LSB DT (LSB) 1,326,300 0 20 40 60 Monitoring time (s) Vs = Vsig + Vr 1,326,980 1,326,970 Vsig DT (LSB) Vs DTc (LSB) 1,326,960 Vr 5 LSB 1,326,950 0 20 40 60 Monitoring time (s) Monitoring time (s) Low-frequency noise-removing mechanism Analog switch CMOS input buffer Vs TAD DT (Vin) Vin Vr 1/2 Vs CKs (1 kHz) DTc Vr Block diagram of test circuit (a) Before correction (Vs = 2.50 V) (b) After correction(Vs = Vr = 2.50 V) Vs can remove any low-frequency noise. Low-frequency noise removing result Vr (with 1000-data moving average processing)