Computer Systems Organization & Architecture Chapter 1 Part 9 Adders and Subtractors

1. Computer Systems Organization & Architecture Chapter 1 Part 9 Adders and Subtractors

2. Used to perform addition, subtraction, multiplication, and division (sometimes) Combinational circuit (no memory) Adders

3. Half adder Inputs two 1-bit values, X and Y Outputs their 2-bit sum as bits C and S C is carry S is the sum Adders

4. Half Adder

5. To add larger numbers must carry information from previous bits Full adder has 3 inputs: Two data inputs One carry input Has same outputs as half adder C is carry S is the sum Function implemented: Full Adders

6. Full Adder

7. Create by connecting output C of one adder to Cin of the next adder. Called ripple adder n-bit adders

8. Last adder provides a carry out for the 4-bit addition. First adder is a full adder with externally generated carry in. Used by the CPU for some operations A 4-bit comparator Schematic symbol

9. Ripple adder worst case: X = 1111, Y = 0001. C = 1, S = 0 Each adder must wait for the result from the previous adder before its computation is valid Each full adder has a slight delay before its value is valid These delays add up as the carry bits ripple from right to left Propagation Delay

10. Is there more than one way to do addition? two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c1 = b0c0 + a0c0 +a0b0 c2 = b1c1 + a1c1 +a1b1 = b1(b0c0 + a0c0 +a0b0) + a1(…)+a1b1 c3 = b2c2 + a2c2 +a2b2 = b2(b1c1 + a1c1 +a1b1c2) + a2(…)+a2b2 c4 = b3c3 + a3c3 +a3b3 = b2(b1 (b0c0 + a0c0 +a0b0) + … Now there is no propagation delay! Not feasible! Why? ripple carry adder is slow Fan-in grows exponentially with the number of bits!

11. An approach in-between our two extremes Motivation: If we didn't know the value of carry-in, what could we do? When would we always generate a carry? gi = ai bi When would we propagate the carry? pi = ai + bi Recall the equation for the carryOut: Cout = bCin + aCin + ab Cout = ab + (a + b)Cin Define a generate function: gi = ai bi Define a propagate function: pi = ai + bi Then (ci is carryIn for the ith term) Cout = ci+1 = gi + pi ci Carry-lookahead adder ci ai Cin ALU31 Cout si bi ci+1

12. Cout = ci+1 = gi + pi ci Did we get rid of the ripple? c1 = g0 + p0c0 c2 = g1 + p1c1 = c3 = g2 + p2c2 = c4 = g3 + p3c3 = Time: to generate pi and gi takes 1 gate delays To generate AND terms takes one gate delay To generate OR terms takes one gate delay So all carries are available in 3 gate delays Carry-lookahead adder g1 + p1(g0 + p0c0)= g1 + p1g0 + p1p0c0 g2 + p2(g1 + p1c1)= g2 + p2g1 + p2p1c1 = g2 + p2g1 + p2p1(g0 + p0c0) = g2 + p2g1 + p2p1g0 + p2p1p0c0 g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

13. c4 = g3 + p3c3 = all carries are available in 3 gate delays Sum bit: sum = a xor b xor cin + a b cin takes 2 gate delays So entire sum of two n bit numbers can be found in 5 gate delays. Problem: fan-in. If use a 4-bit carry-lookahead adder (see above), then fan-in is 5. Can connect 4 carry-lookahead adders sequentially and get a 16-bit adder with time equal to 11 gate delays: 1 gate delay to form gi and pi 2 gate delays to form each of c4, c8, c12, c15(8 total) 2 gate delays to form s15 All other sum bits and c16 available at or before s15 Takes ripple carry adder 32 gate delays! Carry-lookahead adder: Time g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

14. Carry-lookahead adder: Time c0 generate c1 to c4 g0 to g3 Cin Cout s0 to s3 p0 to p3 c4 generate c5 to c8 g4 to g7 Cin Cout s4 to s7 p4 to p7 generate c9 to c12 c8 g8 to g11 Cin Cout s8 to s11 p8 to p11 generate c13 to c16 (c16 for overflow) c12 g12 to g15 Cin Less s12 to s15 p12 to p15

15. Use principle to build bigger adders • Better: use the CLA principle again! • Use the lookahead technique to carry signals between blocks! • A second level of lookahead is employed • Idea: use propagate and generate signals at a higher level. • Consider the formula for c4 : g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0 • Define P0 and G0 as: P0 = p3p2p1p0 G0 = g3 + p3g2 + p3p2g1 + p3p2p1g0 • Then: c4 = G0 + P0 c0

16. Use principle to build bigger adders • Now consider the formula for c8 : g7 + p7g6 + p7p6g5 + p7p6p5g4 + p7p6p5p4c4 • Define P1 and G1 as: P1 = p7p6p5p4 G1 = g7 + p7g6 + p7p6g5 + p7p6p5g4 • Then: c8 = G1 + P1 c4 • Recall that: c4 = G0 + P0 c0 • So: c8 = G1 + P1 (G0 + P0 c0) = G1 + P1G0 + P1P0c0

17. Use principle to build bigger adders • In the same way define P2, P3, G2 and G3 as: P2 = p11p10p9p8 G2 = g11 + p11g10 + p11p10g9 + p11p10p9g8 P3 = p15p14p13p12 G3 = g15 + p15g14 + p15p14g13 + p15p14p13g12 • Then: c12 = G2 + P2 c8 c16 = G3 + P3 c12 • and: c12 = G2 + P2G1 + P2P1G0 + P2P1P0c0 c16 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

18. Use principle to build bigger adders

19. The first 1st-level block: Calculations c0 g0 = a0 b0 p0 = a0 + b0 P0 g1 = a1 b1 p1 = a1 + b1 a0 G0 g2 = a2 b2 p2 = a2 + b2 b0 g3 = a3 b3 p3 = a3 + b3 a1 P0 = p3p2p1p0 G0 = g3 + p3g2 + p3p2g1 + p3p2p1g0 b1 S0-S3 a2 c1 = g0 + p0c0 c2 = g1 + p1c1 c3 = g2 + p2c2 = g1 + p1(g0 + p0c0) b2 = g2 + p2g1 + p2p1g0 + p2p1p0c0 a3 s0 = a0 xor b0 xor c0 s1 = a1 xor b1 xor c1 b3 s2 = a2 xor b2 xor c2 s3 = a3 xor b3 xor c3

20. Other 1st-level block: Calculations pi = gi = Pj pi+1 = ai gi+1 = Gj pi+2 = gi+2 = bi Cj pi+3 = gi+3 = ai+1 Pj = Gj = bi+1 Si-Si+3 ai+2 ci+1 = gi + pici ci+2 = gi+1 + pi+1ci+1 ci+3 = gi+2 + pi+2ci+2 bi+2 ai+3 = gi+2 + pi+2gi+1 + pi+2pi+1gi + pi+2pi+1pici bi+3 si = ai xor bi xor ci si+1 = ai+1 xor bi+1 xor ci+1 si+2 = ai+2 xor bi+2 xor ci+2 si+3 = ai+3 xor bi+3 xor ci+3

21. For all first-level blocks, need 3 gate delays for all Pi and Gi: all pi and gi takes one gate delay all Pi and Gi and all ci takes two gate delays after pi and gi are calculated For second level block (carry-lookahead hardware): All Ci take 2 gate delays after get all Pi and Gi receive all Pi and Gi after 3 gate delays Return all Ci after 5 gate delays For all first-level blocks, return Sum after 8 gate delays (note that c15 = C4 is the carryout of the adder)! receive Ci (ie, C1 = c4 , C2 = c8 , C3 = c12 , C4 = c15 ) after 5 gate delays All ci are calculated 2 gate delays after Ci is recieved all si takes one gate delay (if xor = 1 gate delay) after all ci are calculated Time

22. Compare: ripple-carry takes 16 X 2 = 32 gate delays. Fan-in for 2-level carry-lookahead: need 1 AND gate of fan-in 5, every other gate has fan-in 4 or less (see previous diagram). Time and fan-in

23. Determine pi,gi Pi, and Gi values of these two 16-bit numbers: a = 0001 1010 0011 0011 b = 1110 0101 1110 1011 gi = 0000 0000 0010 0011 pi = 1111 1111 1111 1011 Where the bits are numbered 15 to 0, left to right P3 = 1 P2 = 1 P1 = 1 P0 = 0 G0 = 0 G1 = 1 G2 = 0 G3 = 0 c15 = C4 = 1 So there IS a carry out when adding these two 16-bit numbers Example

24. Not common Normally use two’s complement to subtract Add the complement of a number using the adder Full subtractor Three inputs: two data and a borrow input Next slide implements the functions: Subtractors

25. Full Subtractor

26. Can be created with adders or subtractors Normally have special circuits Discuss in chapter 8 Multipliers and Dividers