module rtl_example (reset_n, clk, a, b, f, count); input reset_n; input clk;

1. module rtl_example (reset_n, clk, a, b, f, count); input reset_n; input clk; input [7:0] a; input [7:0] b; output [7:0] f; output [7:0] count; reg [7:0] f; // signals written to in always blocks are reg [1:0] state; // declared as reg. will synthesize to FFs reg [7:0] count; // only if the always block is sensitive to // an edge, i.e., posedge clk. reg [7:0] c; // temporary variables, declared as reg if reg [7:0] t; // they are used inside always blocks parameter s0=0, // declaration of states using a parameter s1=1, // (constant) declaration. s2=2; function [7:0] myinc; // functions, once declared, can be input [7:0] x; // called from anywhere, including from reg [7:0] sum; // within always blocks or in assign reg c; // statements. can use "=" inside to integer i; // specify combinational logic. begin c = 1; for (i = 0; i < 8; i = i + 1) // increment implemented begin // by adding "0" with sum[i] = x[i] ^ c; // initial carry = "1". c = c & x[i]; end myinc = sum; end endfunction always @ (*) // unclocked always block, use "=" begin // to specify combinational logic. t = c << 1; f = t + 1; end always @ (posedge clk or negedge reset_n) // clocked always, if (!reset_n) // use "<=". active low begin // asynchronous reset. count <= 8'b00000000; c <= 8'b00000000; state <= s0; // "<=" means signal on end // LHS of equation is fed else // into a register. begin case (state) s0: begin count <= 8'b00000000; c <= 8'b00000000; state <= s1; end s1: begin c <= a + b; // "<=" means signal on count <= count + 1; // RHS of equation comes state <= s2; // from output of end // corresponding s2: begin // register. c <= a - b; count <= myinc(count); state <= s0; end endcase end endmodule

2. reset_n clk module rtl_example 8 8 8 8 8 8 2 clocked always block unclocked always block c 00 01 10 11 0 a + c t <<1 +1 f – b count 00 01 10 11 0 +1 count myinc 00 01 10 11 s1 state s2 state s0