A Case Study of the Rehosting from VHDL to Matlab

1. A Case Study of the Rehosting from VHDL to Matlab Yulong Zou and Yu-Dong Yao Stevens Institute of Technology Jun. 14, 2010 1

2. Outline • Challenging Issues and Solutions • A Case Study of VHDL Code for an ADDER • Next Step 2

3. Challenging Issues and Solutions 3 • Abstraction of Variable Semantics: In VHDL, variables are defined as standard logic vectors and different logic vector may have different length. Solution: use a place to describe each variable in VHDL, instead of a thing only. • Many Unique Keywords in VHDL: entity, architecture, port, in, out, downto, signal, &, and so on. Solution: a path is employed to describe an entity and the corresponding architecture.

4. A Case Study of VHDL Code for an ADDER 4

5. Next Step 5 • To extend XML representation capabilities to handle other VHDL keywords: process, group, file, exit, and so on. • To complete the inference engine, e.g., • to achieve the translation from XML representation to VHDL; • to enable multiple output from XML representation to C /C++.

6. A&Q 6