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Hi-PBD : Hi erarchical P latform- B ased D esign Method ----research & implementation

International Conference on System-on-a-Chip. Hi-PBD : Hi erarchical P latform- B ased D esign Method ----research & implementation. Speaker: Zhihui Xiong. VLSI Lab. National University of Defense Technology. Changsha, China. Jihua Chen , Zhihui Xiong, Sikun Li. Outline. Related Work.

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Hi-PBD : Hi erarchical P latform- B ased D esign Method ----research & implementation

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  1. International Conference on System-on-a-Chip Hi-PBD: Hierarchical Platform-Based Design Method ----research & implementation Speaker: Zhihui Xiong VLSI Lab. National University of Defense Technology Changsha, China Jihua Chen ,Zhihui Xiong, Sikun Li

  2. Outline • Related Work • mainstream VLSI design methodologies • existing co-design environments • drawbacks • Research on Hi-PBD • YH-PBDE: Implementation of Hi-PBD method • Conclusions & Future Work

  3. Related Work • mainstream VLSI design methodologies • Timing-Driven Design: TDD, deep sub-micro ASIC design • Block-Based Design: BBD, supports IP reuse • Platform-Based Design: PBD, supports system reuse, including reuse of IPs, models, tools, libraries and design flows

  4. Related Work (cont.) • existing co-design environments • VULCAN: by R. K. Gupta, 1993, Stanford University. • COSYMA : by R. Ernst, 1996, Tech. Univ. of Braunschweig • since then, others including: Ptolemy, Polis, PeaCE, … • SCE: by D. D. Gajski, 2003, TIMA Lab. France • some commercial tools • Cadence VCC • CoWare N2C • Synopsys CoCentric Studio

  5. Related Work (cont.) • drawbacks • no real separation of design concerns • no separation of function from structure • no separation of computation from communication • little support for Platform-Based Design methodology • mainly support IP level reuse, not system level reuse • only support some phases of SoC design, and little support for the overall phases

  6. Outline • Related Work • Research on Hi-PBD • ideas • overall structure • more words on Virtual Components Level • features • YH-PBDE: Implementation of Hi-PBD method • Conclusions & Future Work

  7. Research on Hi-PBD • ideas first of all, let’s see a “true” story…… One day, Bill Gates discovered a big bag of dollars. However, it is too high to get it directly.

  8. Research on Hi-PBD • ideas first of all, let see a “true” story…… (cont.) After some consideration, he decided to use a ladder.

  9. Research on Hi-PBD • ideas first of all, let see a “true” story…… (cont.) Then, he climbed towards the dollars.

  10. Research on Hi-PBD • ideas first of all, let see a “true” story…… (cont.) Finally, he got the bag of dollars, and became the richest man in the world.

  11. Research on Hi-PBD • ideas now, a similar thing happens with SoC design …… since too many things to be done: • Hw/Sw partitioning • co-simulation • performance evaluation • hardware & interface synthesis • embedded software generation • ……

  12. Research on Hi-PBD • ideas now, a similar thing happens with SoC design …… • hardware & interface synthesis • embedded software generation • Hw/Sw partitioning

  13. Research on Hi-PBD • overall structure • 3 design levels • 2 design mappings • 1 platform library • system modeling level • design planning • to achieve system level reusability • virtual components level • virtual-real synthesis • real components level

  14. Research on Hi-PBD • overall structure (cont.) system modeling level (SML) • describes function and performance of SoC at algorithm level • system modeling based on CTG model • CTG: Constrained Taskflow Graph • Hierarchical FSM + coarse grained CDFG + performance constraint

  15. Research on Hi-PBD • overall structure (cont.) Virtual Components Level (VCL) • abstracts the RTL SoC system architecture • serves as a connecting link between the system modeling level and real components level • avoids direct synthesis from system model to the final SoC target • virtual hardware components (VHwIPs) • virtual software components (VSwIPs) • virtual communicator components (VCommuIPs)

  16. Research on Hi-PBD • overall structure (cont.) Real Components Level (RCL) • RTL Hw/Sw SoC system • HW part: hardware accelerator modules (such as co-processor, DSP, ASIC), Input/Output controller devices • SW part: RTOS, device driver, application processes • fast prototyping based on FPGA board, for RTL simulation and performance analysis

  17. Research on Hi-PBD • overall structure (cont.) 2 design mappings ---- mapping L0-L1 • the mapping from System Modeling Level to Virtual Components Level, we call it Design Planning • some tasks are partitioned to hardware • other tasks are partitioned to software

  18. Research on Hi-PBD • overall structure (cont.) 2 design mappings ---- mapping L1-L2 • mapping from Virtual Components Level to Real Components Level, we call it Virtual-Real Synthesis • virtual hardware is synthesized to real (RTL) hardware • virtual software is synthesized to embedded process • virtual communicator is synthesized to On-Chip Bus

  19. Research on Hi-PBD • more words on Virtual Components Level virtual component model • behavior part • structure part • construct “virtual design” • for partitioning • for synthesis • for software generation • for co-simulation • for verification & evaluation

  20. Research on Hi-PBD • more words on Virtual Components Level (cont.) modeling hardware at VCL • a simple module (adder) • a more complex module • modeling of these two modules

  21. Research on Hi-PBD • more words on Virtual Components Level (cont.) modeling software at VCL • wrap software process using SystemC module • process (task) template in uC/OS II • adder example process • wrapped adder • variables and external APIs are mapped to ports • normal statements are mapped to behaviors • RTOS services are mapped to SystemC core

  22. Research on Hi-PBD • more words on Virtual Components Level (cont.) modeling communication at VCL • connects multiple V.C.s • message transmitting flow step1: consumer 2 requires data from producer 0 step2: communicator transmits the message to producer 0 step3: producer 0 receives data requirement step4: producer 0 sends data to consumer 2 step5: communicator transmits the message to consumer 2 step 6: consumer 2 receives the data

  23. Research on Hi-PBD • features • hierarchicaldesign flow • 3 design levels • 2 mappings • supports system levelreuse well • enables reuse of design templates on each design level • enable reuse of mapping process & mapping results • achieves separation of design concerns • separation of function from structure • separation of computation from communication

  24. Outline • Related Work • Research on Hi-PBD • YH-PBDE: Implementation of Hi-PBD method • architecture • performance & power estimation • snapshots • Conclusions & Future Work

  25. YH-PBDE: Implementation of Hi-PBD method • architecture • modeling/simulation & mapping tools • do modeling and simulation at the three design levels • do mapping between design levels • helper tools • platform manager • for system level reuse

  26. YH-PBDE: Implementation of Hi-PBD method • performance & power estimation • apply different estimation methods for different levels • estimation at System Modeling Level • based on combination of SimpleScalar and Sim-Wattch • and made some improvements • estimation at Virtual Components Level • establish performance character for each virtual component • establish power character for each virtual component • while simulating on SystemC core, calculate performance and power • estimation at Real Components Level • performance are estimated via FPGA development suites • Power(system) = Power(Sw) + Power(Hw)

  27. YH-PBDE: Implementation of Hi-PBD method • snapshots system modeling, task attribute editor

  28. YH-PBDE: Implementation of Hi-PBD method • snapshots (cont.) system modeling, taskFSM editor

  29. YH-PBDE: Implementation of Hi-PBD method • snapshots (cont.) virtual components editor

  30. YH-PBDE: Implementation of Hi-PBD method • snapshots (cont.) real components editor

  31. YH-PBDE: Implementation of Hi-PBD method • snapshots (cont.) partitioning interface

  32. Outline • Related Work • Research on Hi-PBD • YH-PBDE: Implementation of Hi-PBD method • Conclusions & Future Work

  33. Conclusions & Future Work • Conclusions • Hi-PBD method improves high level design efficiency • Introduction of Virtual Components Level makes it more easy to do SoC high level design • The implemented environment supports Hi-PBD well • Future Work • to do more research on Virtual-Real Synthesis • to do more work on embedded software generation • to do more work on power-aware Hi-PBD method

  34. Thank you

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