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Development of the input circuit for GOSSIP vertex detector in 0.13 μ m CMOS technology.

This research delves into designing the input circuit for the GOSSIP vertex detector in 0.13μm CMOS technology. It outlines the principles of operation and features of the GOSSIP detector, emphasizing the single electron efficiency and power consumption requirements for the readout circuit. Details on the prototype of the input circuit, including evaluation of parasitic capacitances and considerations for stability and power dissipation, are explored. Notable aspects covered include the charge-sensitive preamplifier gain, operational amplifier configuration, and feedback capacitor specifications. The study aims to optimize the input circuit performance in line with detector specifications and technology capabilities.

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Development of the input circuit for GOSSIP vertex detector in 0.13 μ m CMOS technology.

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  1. Development of the input circuit for GOSSIP vertex detector in 0.13 μm CMOS technology. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam, The Netherlands. September 28, 2006.

  2. Outline • GOSSIP detector: principles of operation and features. • Inputs and requirements for the design of the input circuit. • The prototype of the input circuit. • Conclusions and plans.

  3. GOSSIP detector: principles of operation. Gas On Slimmed Silicon Pixel (GOSSIP) is a vertex detector combining a thin gas layer as signal generator with a CMOS readout pixel array. Cathode (drift) plane Cluster1 Cluster2 1 mm, 400 V Cluster3 Integrated Grid (InGrid) Z 50 μm, 400 V Y Slimmed Silicon Readout chip X Input pixel 50 μm • - projection of the track. • 3D reconstruction of the track..

  4. GOSSIP detector: main features. GOSSIP detector. Hybrid pixel detector. Cathode foil. Thickness is 1 μm . Chip pixel unit cell with bump bonding. Silicon sensor. Thickness is 250 μm . Integrated grid (InGrid) Thickness is 1 um . Chip pixel unit cell. Slimmed (polished) readout chip. Thickness is 50 μm . Readout chip. CONTRA - spark protection • PRO • can operate up to fluences of 1016 cm-2 • low material budget • -negligible detector leakage current • -low detector parasitic capacitance

  5. i(t) ion component electron component 5 - 30 ns Inputs and requirements for the design of the input circuit. Single electron efficiency. 1 0.9 0.8 0.7 0.6 0.5 Gain = 8000 -the low-threshold operation (THR < 400 e) is required. Gain = 4000 Gain = 2000 0 1000 500 1500 2000 Threshold, electrons Shape of the detector current. - motion of ions mainly determines the detector current.

  6. Inputs and requirements for the design of the readout circuit. Single electron drift time measurements (simulations) • time resolution • σtime walk = 2 ns (100 μm) . Gain = 8000 Gain = 4000 Entries Gain = 2000 0 2ns 4ns 6ns 8ns 10ns 12ns 14ns Measured drift time Power consumption. • low power dissipation • reduction of the material budget . Analog: 2 μW / pixel. Total: 100 mW / cm2 or 200 mW / chip.

  7. Inputs and requirements for the design of the readout circuit. • the high sensitive analog circuit must be effectively isolated from the high speed switching lines. Analog-digital crosstalk. Pixel pitch and the chip size. • pixel pitch 55 μm x 55 μm . • - sensitive area a matrix of • 256 x 256 pixels ( 1.98 cm2). 256 pixels · 55 μm =1.4 cm 256 pixels · 55 μm =1.4 cm Readout chip 55 μm

  8. The prototype of the inputcircuit. Parasitic capacitance at the input of the front-end circuit . Power Consumption Noise Cdet Speed Cdet= Cpar= Cp-grid+ Cp-p+ Cp-sub , where Cp-sub is pad-to-substrate capacitance Cp-grid is pad-to-InGrid capacitance Cp-pis pad-to-pad capacitance InGrid Cp-grid Cp-grid Cp-grid Cp-p Cp-p Substrate Input pad Cp-sub

  9. The prototype of the inputcircuit. Evaluation of the input parasitic capacitances in 0.13 μm CMOS technology . Pad-to-pad capacitance (Cp-p). Pad-to-InGrid capacitance (Cp-grid). 2 1.5 1 Cp-InGrid,fF 0.5 0 2.5 2 1.5 Cp-p,fF 1 0.5 0 0 5 10 15 20 pad-to-pad distance, μm 0 10 20 30 40 50 size of the pad, μm Pad-to-substrate capacitance (Cp-sub). 60 50 40 30 Cp-sub, fF 20 10 0 • input parasitic capacitance ≈ 10 fF. 0 10 20 30 40 50 size of the pad, μm

  10. The prototype of the inputcircuit. Gain in the charge-sensitive preamplifier with a very low parasitic capacitance at the input (Cpar → 10 fF). Cfb 1 Charge-to-voltage gain≈ Cfb Qin Rfb ≈ 10 fF Output Cpar A Iin(t) Cfb >> Cfb = 1fF ??? - Stability ? - Physical layout ? Cpar A ≈130 Open loop voltage gain of the OPAMP Coaxial-like layout of the input interconnection. Input pad Cpar = 10 fF…50 fF LM Ground plane M6 Ground Output M3 Cfb=1 fF M2 M1 Parasitic metal-to-metal fringe capacitance. Substrate

  11. The prototype of the inputcircuit. Stability of the charge-sensitive preamplifier with a very low parasitic capacitance at the input (Cpar → 10 fF). • The scheme of F.Krummenacher no need for the leakage current compensation 2Ip Silicon sensor Cfb Cfb=1 fF Output Ileak > 1 μA Output Input Cpar Cpar Iconst Ileak +Ip Ip Cint • This circuit becomes unstable when • Cpar → 10 fF • This circuit demonstrates a safe phase margin even when • Cpar → 10 fF

  12. The prototype of the inputcircuit. DC feedback in the charge-sensitive preamplifier. Virtual resistor Rfb = 80 MΩ Input Output Vdd=1.2 V - allows for discharging of the feedback capacitor. Rfb = 1/gmM1 + 1/gmM2 = 80 MΩ - biases the input of the circuit. Statistical spread of the offset at the output σ(δUoutDC) = 20 mV (170 e-). M5 M3 M4 M2 M1 Vb1 Ib=1 nA Cfb =1 fF Output Input Vb2 M8 M6 M9 M7

  13. The prototype of the inputcircuit. The operational amplifier. Output Input OPAMP Vdd=1.2V M5 M6 Transfer function Uout / Uin = A(jω)= Ao/(1+jωτ) = 130/(1+jω●14 ns) Bias current Ib1+Ib2=1 μA + 0.2 μA =1.2 μA Power dissipation P=1.2 V ● 1.2 μA = 1.5 μW M7 Output Ib2=0.2 μA M3 M4 Vb3 Input M1 M2 Vb2 Ib1=1 μA

  14. The prototype of the inputcircuit. Pulse response and noise. Cfb = 1fF Qin Rfb = 80 MΩ Output Iin(t) Cpar Ib1=1 μA • response peaking time is • 5 ns…30 ns. • ENC ≈ 60..80 e- (RMS) • even with low bias current (Ib1=1 μA) and • fast peaking time. A(jω)=Ao/(1+j●ω●τo) δ-pulse response of the preamplifier 3 ●τo ≈ 5 ns … 30 ns Cpar Peaking time = Ao ●Cfb 1+ Cpar + Cfb 450 440 430 U, mV 420 410 400 1 Qin ● Amplitude = Cpar + Cfb Cfb 1+ Ao ●Cfb Decay of the signal is t exp Rfb● Cfb 100 150 200 250 300 350 Time, ns

  15. The prototype of the inputcircuit. Physical layout aspect. Floating P-well for analog NFETs. VDD_ana Guard rings GND GND_ana Analog N-type FET area Digital N-type FET area Analog P-type FET area P-well P-type substrate N-well substrate current - Triple well layout let us better isolate digital and analog parts of the chip. GOSSIPO chip, submitted on December 12, 2005.

  16. The prototype of the inputcircuit. Principal Block Diagram of the prototype. • Objectives for the first submit. • Operation of the proposed front-end circuit • -stability of the preamplifier • -pulse response • -noise • -channel-to-channel spread. • 2) Cross-talk between the high sensitive analog circuit and high speed switching CMOS blocks. Charge sensitive preamplifier Voltage follower Cfb ≈ 1fF Rfb ≈ 80 MΩ Input 1 Ct ≈ 3.3 fF Cpar ≈ 30 fF CMOS Comparator CMOS Counter Charge sensitive preamplifier Outputs Cfb ≈ 1 fF Rfb ≈ 80 MΩ Input 2 Ct ≈ 3.3 fF Start Cpar ≈ 30 fF Stop Clock

  17. The prototype of the inputcircuit. Measurements. δ-pulse response of the preamplifier. Qin = 1000 e- δ-pulse response of the preamplifier. Qin = 410 e- - The preamplifier with (Cpar = 35 fF and Cfb = 1 fF) demonstrates a stable operation and an expected pulse response and noise. ENC = 60 e- (RMS) .

  18. The prototype of the inputcircuit. Measurements. δ-pulse response at the output of the CMOS comparator. Qin = 410 e-. Threshold = 300 e-. • The channel-to-channel spread of the threshold is • σTHR ≈ 160 e- • ( consistent with simulations).

  19. The prototype of the inputcircuit. Measurements. Clock signal is running at 100 MHz. The output of the comparator. Threshold = 300 e- - no significant crosstalk between the high sensitive input and the 100 MHz clock line.

  20. Conclusions and plans. • Front-end readout circuit of the GOSSIP chip will benefit from the low detector parasitic capacitance and no need to compensate for the leakage current. • The first prototype of the fast (40 ns peaking time), low-noise (ENC = 60 e- (RMS) and low-power (2 μw per channel) input circuit for the GOSSIP chip has been successfully implemented in 0.13 μm CMOS technology. • Owing to the triple well layout used in the prototype, the high sensitive analog inputs have been effectively isolated from the high speed switching gates. • A new prototype featuring TDC-per-pixel concept will be submitted in the end of 2006.

  21. Additional slide. Protection against discharges. Layout of the input pad 20um Polymide High Resistive Amorphous Silicon 3um Oxide Metal layer TD Metal layer LM Rprot ≈ 1MΩ Qdischarge Rfb Output A Cp-sub≈ 10fF Cp-grid≈ 0.5fF - protective resistor causes neither signal distortion nor noise increase as long as Rprot●Cp-grid is less than 1ns.

  22. Additional slide. Integrated Grids.

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