A Primer on CMOS Technology

1. A Primer on CMOS Technology

2. Objectives: 1.To Introduce about CMOS technology

3. Basic CMOS Fabrication Flow Fabrication Steps Lithography

4. Key Characteristics: • Bulk Process • Twin Wells • Shallow Trench Isolation • Poly gate material • Lightly doped Source/Drain extensions • Salicidedgate,drain source areas • Subtractive metarialzation

5. The Fabrication Steps FEOL BEOL

6. Front-End-Of-Line : 1.Initial Wafer • Either p-type or n-type wafer • Epitaxial layer of gentle doping

7. 2.n-well Formation • A mask is used to define the geometry of n-well • Donor atoms are implanted into indicated region • This will be p-channel MOSFET

8. 3.p-well Formation: • Do the complementary job of n-well formation

9. 4.Active area definition: • MOSFETs & diffusion areas are defined by subsequent mask • Thin buffer oxide layer SiN layer is used to cover the entire surface

10. 5.Shallow trench isolation: • Trenches are cut into the bulk materials • Trenches filled up with oxide materials • Remove the materials by using Chemical mechanical polishing • CMP is used to get most planer surface which is essential for photolithography process

11. 6.Gate dielectric Formation: • The Wafer is layered by extremely thin (2nm-5nm) oxide layer

12. 7.Polysilicon Deposition and patterning: • The entire surface is covered with poly silicon film(200nm)

13. 8.n-channel source/drain extension: • N-type material is imposed to extend the source & drain

14. 9.p-channel source/drain extension • Do the complementary job of n-channel

15. 10.Side-wall or oxide spacers: • An oxide layer is deposited and etched away to leave an insulating wall

16. 11.n-type doping: • A heavier and deeper implant is used to make drain and sources of the n- channel MOSFETs • Side wall spacers prevent penetration of doping atoms

17. 12.p-type doping: • Complementary job of n-type doping is done here

18. 13.Salicidatioin : • Wafer is covered by thin Highly conductive silicide film • That serve lower electrical resistivity to source drain and gate

19. Back-End-Of-Line: 1.First interlevel dielectric : • Layer of Silicon dioxide is deposited • Another CMP planarization step is done to make layer the first interevel dielectric

20. 2.Contact plug formation: • Mask CONTACT defines the region where metal shell connect to adiffusion or polysilicon region • Tungsten is deposited to form the plug

21. 3.Deposition of patterning of first metal layer: • Metal layer is deposited entire the layer surface • Metal layer removed selectively to leave behind those parts that are defined metal1 mask

22. 4.Second inter level dielectric: • The second interlevel dielectric deposited and planarized

23. 5.Via plug formation: • Mask via1 defines those location where a first metal structure shall connect

24. 6.Deposition of patterning of second metal layer: • The Second layer of metal is obtained by way of subtractive metalization

25. 7.Third interlevel dielectric followed by via plug formation: • Dielectric deposition , planarization , plug formation , metal deposition and metal patterning is done in this step • Two mask is required per metal layer

26. 8.Deposition of patterning of third metal layer : • Topmost metal layer

27. 9.Overglass and bond pad openings : • The Wafer surface is covered by a Layer of Silica

29. Process Monitoring: • Capcitance-Voltage Characteristics are obtained from MOSCAP • The Resistivity of all Conductive layer is determined Van der Pauw structure . • Fault Wafers are detected and sorted out

30. Photolithography

31. Photolithography has Four major Parts: 1.An Illumination Source 2.A mask 3.An exposer subsystem 4.Photoresist Materials

33. A Practical Photolithographic machine:

34. Traditional optical Lithography: • 546 nm E-line • 436 nm G-line • 405 nm H-line • 364 nm I-line

35. Deep UV Lithography: • 248 nm (KrF6) • 193 nm (ArF6) • 157 nm (F2)

37. Resolution Enhancement Techniques: • 1.Phase Shift Masks: • Improving line Separation by cancelling out light waves using destructive interference • Illumination must be from a partially coherent source.

39. 2.Off-axis Illumination: • Like as Phase shift masking • But there is no extra phase shifter • Slightly tilted illumination axis

40. 3.Optical Proximity Correction: • Applies inverse distortion to the mask to precompensate the inperfection • Overaccutuated corners such as serifs and hammer heads are typical for OPC 4.Computerized resolution enhancement : PSM & OPC are used in computerized way in high volume high repetitive layout ( like RAM)

42. Post Optical Lithography: • 1.Electron beam direct write lithography: • Layout pattern get written in photoresist layer by an electron beam • It is too slow for mass production • 2.Nano imprint lithography: • Here Photoresist is not used • Patterns are printed on polymer coating by pressing a stencil on the wafer surface

43. Some Change Has been made in Fabrication Industry: • Copper Has Replaced Aluminum as interconnect material:

44. First Fabrication process with Cu as Interconnect material :

45. Low-permittivity interlevel dielectrics are replacing Silicon-di-oxide: • Low permittivity dielectric is using for • 1.Good mechanical strength • 2.Process Compatibility • 3.Thermal Stability • 4.Low moisture absorption

46. Intel’s 65 nm processed material where Carbon doped oxide CDO (€r=2.9)is used as interlevel dielectric instead of Silicon-di-Oxide(€r=3.9)

47. THE END