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OCP-IP Debug Status and Plans

OCP-IP Debug Status and Plans. DAC System and SoC Debug Workshop, June 8, 2008 Dr. Neal Stollon, HDL Dynamics neals@hdldynamcs.com. OCP Debug Working Group. OCP is neutral On Chip Protocol for SoC IP connection

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OCP-IP Debug Status and Plans

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  1. OCP-IP Debug Status and Plans DAC System and SoC Debug Workshop, June 8, 2008 Dr. Neal Stollon, HDL Dynamics neals@hdldynamcs.com

  2. OCP Debug Working Group • OCP is neutral On Chip Protocol for SoC IP connection • WG focus on defining debug related signaling between cores and other embedded subsystems • Leverage other work for IOs (JTAG, Nexus), APIs, etc. • Defined subset architecture for on chip debug Baseline Sockets 1149.1 JTAG Debug resets Generic Processor debug handshakes Cross Trigger Interfaces Synchronize Trace/Debug Trace Triggers TimeStamp Interfaces Power Management Debug Security OCP 2.1 Socket OCP Debug Socket OCP Fabric b OCP Fabric RISC RISC Mem Ctrlr Mem Ctrlr DSP DSP RAM RAM Other IP Other IP Other IP Other IP Standardized transfer socket Master or slave, with optional bursting, thread signals not be same Debug Features For all sockets are optional

  3. Debug Socket for Multi-Core Debugging OCP-IP Debug WG announces the release of its Debug Standard.  The new standard identifies Basic and Extended sets of socket level signals for debugging of multiple processor cores connected with the OCP interface.  The standard represents a breakthrough allowing designers to distribute debug signals as part of the system interface scheme; rather than wired separately from the data path as had been previously been the case. This innovative new approach greatly enhances system providers ability to prepare multi-core debug hardware and software.

  4. What is in the Debug Specification? OCP Interface for Basic Debug Signals • Debug Control and Run Control for Cores • Consistent (multiple) processor software debugger interfaces • Cross-Triggering between Multiple Cores and Events • Scalable to on-chip/off-chip cross triggering • Trace Interface • Bus traffic observation (system trace) and control (triggering)‏ • New classes of debug errors (different from system errors)‏ OCP Interface for Extended Signals (Special features) • Performance Monitor • Time-stamping • Power Monitoring voltage islands, gated clock islands • Security islands Of huge valuein final silicon

  5. Debug-IP HW connections to SoC: 1 CORE-INTERFACE: interfaces to core IP-block debug data/control proprietary IO 2 BUS-INTERFACE: interface to a bus traffic [event/trace data collect, compression and triggering] 3 CROSS-TRIGGER INTERFACE: to other debug-IP blocks [event-synch.] 4 PIN-INTERFACE CONTROL: IF to JTAG for debug control to analyzer/debugger software. 5 PIN-INTERFACE DATA: interface for high speed data [like Nexus] Debug software API for information transfer and display: A. System Debug SW API interface B. EDA API interface – block and system level verification (ESL, RTL)‏ CHIP Cross trigger IF 3 OCP Bus fabric Bus test socket 1 Core Debug IF Trace IF 2 Memory-mapped JTAG-mapped Nexus-mapped Debug-IP registers Debug IF 4 5 Nexus data-trace JTAG control Debug Software SYS API EDA API A B Debug Hardware Environment

  6. 3rd party CPUDebugger 3rd party DSPDebugger NEW OCP Debug Standard Basic OCP Debug Interface Standard Debug API (SPRINT)‏ Extended OCP Debug Interfaces OCP Debug Compatible fabric B U S F A B R I C CPU Target Description IP-XACT, XML Access HW Debug HW HWIP Target Server DSP The SPRINT software standard is related to our work as a general debug functionality description for multiple processors.

  7. Analysis tools JTAG TAP TDO TDI CrossTrigger Nexus TAP JTAG JTAG Bus Analyzer PM OCP DC Control Chain Compliant DC PM core DC Bus TAP Analysis Chain PM PM Arbitration Bus Fabric Other Cores Bus Master JTAG System Debug Instrumentation OCP Example • On-Chip Analysis • Bus Trace OCP analysis • Complex Cross-Triggering • Performance Monitoring (PM) • Debug Control (DC) • Bus Master Transactors • Integrated processor debug • OCP Debug Spec is in process of release

  8. OCP Debug Standard Advantages Simplifies debug - Standardized Basic OCP core Debug Socket Facilitates Debug Hardware and debugging Software offered as standard IP Opens implementation and support of (heterogenious) processors Proprietary Debug solutions supported - Need just OCP Debug wrapper Fixed OCP debug interface, compatible to multitude of debug interconnects (I.e. Nexus, serial buses, cross bar, NoC, etc)‏ High initial uptake of the new standard in the OCP-IP community

  9. OCP Debug Information • OCP public white papers are at: www.ocpip.org/socket/whitepapers/ • OCP members get the standard at: www.ocpip.org/members/ocpspec/ • OCP membership admin: admin@ocpip.org • Non-members can access this standard using an on-line, click-through research License

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