Upper Bounding Fault Cover age in Stafan

1. Upper Bounding Fault Coverage in Stafan Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn, AL 36849 Soumitra Bose Vijay Gangaram Intel Corporation, Design Technology, Folsom, CA 95630 Presented at 24th IEEE VLSI Test Symposium, April-May 2006 See full paper at: http://www.eng.auburn.edu/~vagrawal/TALKS/vts06_bose.pdf VLSI D&T Seminar, Fall 06

2. Outline • Problem statement and motivation • Background • Upper bounding algorithm • Benchmark results • An application: test-point insertion • Conclusion VLSI D&T Seminar, Fall 06

3. Problem Statement and Motivation • A fault simulation problem • Large non-scan or partial-scan circuits • Long functional verification vector sequences • Objective: • Find compact high fault coverage vectors for testing • Find test points for DFT • Motivation • Exact fault simulation is too expensive • Statistical fault simulator is a useful tool, but needs accuracy • In coverage estimation • In identifying faults not detectable by vector sequence VLSI D&T Seminar, Fall 06

4. Dominator Fanout stem Background • Approximate fault simulation • Per-vector analysis • Critical path tracing (CPT), Abramovici et al., IEEE D&T 1984. • Necessary conditions, Akers et al., ITC 1990. • Post-simulation analysis, Stafan, Jain and Agrawal, IEEE-D&T 1985. • Dominator analysis in ATPG, Kirkland and Mercer, ITC 1987. Fault detection at fanout stem depends on signal states in this part and the observability of the dominator. VLSI D&T Seminar, Fall 06

5. Stafan: A Tutorial Example Incorrectly detected faults OB0=1.0, OB1=0.0 (observabilities) C0=0.4, C1=0.6 (controllabilities) S=0.4 (sensitization count) sa0 sa1 Detected fault 11001 sa1 00000 11001 C0=0.4 C1=0.6 sa1 sa1 C0=1.0 C1=0.0 OB0=1.0 OB1=1.0 C0=0.4 C1=0.6 S=1.0 00110 OB0=1.0 OB1=1.0 C0=0.6, C1=0.4 S=0.6 OB0=0.0 OB1=1.0 OB0=1.0, OB1=0.0 PD: Prob(sa0 detected) = C1 × OB1, Prob(sa1 detected) = C0 × OB0 Threshold detection by N vectors: 1 – (1 – PD)N ≥ 0.5 VLSI D&T Seminar, Fall 06

6. A Circuit Requiring Dynamic Analysis Vector-less static analysis can identify redundant stem faults in the previous example. Stem requires vector-specific analysis Dominator When only 00 and 11 patterns occur on these lines, the stem will be unobservable VLSI D&T Seminar, Fall 06

7. Upper Bounding Algorithm • Structural Analysis • For each fanout stem identify dominator set (gates on paths between the stem and its dominator) • Based on the inversion parities of paths in the dominator set determine stem observability conditions • Monitor Ocurrence of Selected Signal States During Logic Simulation • For a gate, set of input states that forbids path sensitization • For a fanout stem with all same parity paths, set of off-path signal states that forbids sensitizstion of any path • For a fanout stem with different parity paths, set of off-path signal state that simultaneously sensitizes diffrenet parity paths • Similar conditions derived for mixed parity paths • Total number of conditions: O(2×k×N), k = average fanin of gates, N = number of gates VLSI D&T Seminar, Fall 06

8. Algorithm: Fanout Reconvergence (I) Portion of c17: Fanout G1 reconverges with same inversion parity at G5. Same vector applied twice: 11 G2 00 11 11 G1 11 G5 00 sa0 00 sa1 G3 11 Detected faults not detected by stafan Negative errors: G1 output found unobservable. Structural analysis: Stem G1 has two {G2 and G3} same parity paths. Signal monitoring: Only pattern 0XX0 can make stem G1 unobservable  G1 is observable. VLSI D&T Seminar, Fall 06

9. Algorithm: Fanout Reconvergence (II) Portion of c17: Fanout I2 reconverges with different inversion parities at G4. Undetected fault detected by stafan 10 I1 01 G0 sa0 G4 10 I2 11 11 10 I4 G2 00 G1 11 I3 Positive error: When observable fanouts of I2 are treated as independent. Structural analysis: Fanouts paths {G0, and G1-G2} have different parities. Signal monitoring: Propagation through G0: {I1=1 and (I3=0 or I4=0)} = false Propagation through G1-G2: {(I3=1 and I4=1) and I1=0} = false  I2 is unobservable VLSI D&T Seminar, Fall 06

10. Results: Benchmark Circuits * Original stafan; different from “vanilla estimate” in the paper, which is an improved stafan. VLSI D&T Seminar, Fall 06

11. Fault Coverage of c2670 Error in upper bound estimate varies with coverage: Peak error of about 12% after 8 vectors and 53% coverage. VLSI D&T Seminar, Fall 06

12. Application: Scanout Selection • Given large functional sets, each with ~106 vectors: • low individual vector set coverage • high cumulative coverage • set of potential observation (scanout) points find minimal observation points that maximize coverage. • Exact solution: fault simulation with no fault dropping. • Conventional fault simulation takes several days. • Estimate fault detection status for every fault at every potential observation point. • Find a minimal subset of candidates that covers all faults. VLSI D&T Seminar, Fall 06

13. Application: Scanout Selection Note: Fault simulation runtimes assume fault dropping. VLSI D&T Seminar, Fall 06

14. Conclusion • Estimation errors due to reconverging fanouts: • Positive: Undetected faults estimated as detected. • Negative: Detected faults estimated as undetected. • Upper Bounding improvements: • Positive errors reduced by dominators and monitoring • Negative errors reduced by reconvergence analysis • Useful for • Test development • DFT – test point selection • Structural analysis of dominators and signal monitoring can reduce fault detection errors for non-random functional input sequences; to be discussed in a forthcoming paper. VLSI D&T Seminar, Fall 06

15. ITC’06: Improved Stafan – Average, and Upper/Lower Bound Estimates VLSI D&T Seminar, Fall 06