Introductory project

1. Introductory project

2. Development systems • Design Entry • Foundation ISE • Third party tools • Mentor Graphics: FPGA Advantage • Celoxica: DK Design Suite • Design Synthesis • XST: Xilinx Synthesis Technology • Mentor: Leonardo Spectrum • Synplicity: Synplify Pro • Celoxica: DK Design Suite • Simulation • Mentor: Modelsim • Aldec: Active-HDL • Celoxica: DK Design Suite

3. Design Entry Schematic Hardware description language (VHDL, Verilog) Intellectual Property IP blocks Xilinx CoreGen Design Synthesis High level description -> Circuit Design Flow

4. Design Verification Behavioral Simulation Checking high level description of the circuit Functional Simulation Checking synthesized circuit Timing Simulation Static Timing Analysis Searching critical paths In-Circuit Verification Design Flow

5. Optimization (NGDBuild) Merge multiple design files into a single netlist Mapping (MAP) Group logical symbols from the netlist (gates) into physical components (slices and IOBs) Design Flow

6. Place & Route (PAR): Place components onto the chip, connect the components, and extract timing data into reports Bitstream Generation (BitGen) Create configuration file Design Flow

7. Create new project • Select:File-> New Project • Choose project directory and name (myand2) • Set top-level source type to HDL

8. Select: Family: Spartan3E Device: XC3S500E Package: FG320 Speed -5 Synthesis tool: XST Simulator: Modelsim-SE Mixed Preferred Language: VHDL Set Device Properties

9. Click New Source… Select VHDL Module from the list Choose File name (myand2) Create new source

10. Set two inputs (a,b) and one output (c) Define Module

11. Project Navigator • Source files • Built-in editor / Report summary • Processes / Utilities • Console

12. Simple VHDL source

13. Right click myand2 - behavioral in the sources window and select New Source Select VHDL Test Bench from the list Choose File name (myand2_tb) Create Testbench

14. Associate testbench

15. From the Sources for: list select Behavioral Simulation Open myand2_tb Find testbench files

16. Create stimulus

17. Simulation • In the Processes for Source window open ModelSim Simulator • Right click Simulate Behavioral Model and select Properties…

18. Set Simulation Resolution to 1ns Set Simulation Properties

19. The user interface of the ModelSim VHDL simulator

20. Compile, Compile All, Simulate, Break • Restart, Run length, Run, Continue Run, • Run –All, Step, Step Over, Profiling

21. Insert Cursor, Delete Cursor • Previous Transition, Next Transition • Zoom In/Out, Zoom Full • Zoom to Active Cursor

22. Set Sources for to Implementation Select myand2 - Behavioral In the Processes for window double click Synthesize - XST Design Synthesis

23. View RTL Schematic

24. View Technology Schematic

25. Right click myand2 - behavioral in the sources window and select New Source Select VHDL Test Bench from the list Choose File name (myand2) Create Implementation Constraints

26. In the Processes window open User Constraints Select Floorplan I/O – Pre-Synthesis Assign Package Pins

27. Set Loc a: H18 b: G18 c: J14 Assign Package Pins

28. In the Processes for window double click Implement Design Check Place and Route Report for LOCed IBUFs/IOBs Implement Design

29. Right click Generate Programming File in the Processes for window and select Properties… Set Startup Options / FPGA Start-Up Clock to JTAG Clock Double click Generate Programming File Set Programming File Properties

30. Attach and Turn On Nexys2 board Start Digilent / Adept / ExPort Click Initialize Chain Bypass configuration ROM Configuring the device

31. Browse to the project directory Select myand2.bit Click Program Chain Test your first circuit implemented on FPGA Configuring the device