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Memory Organization and Interfacing

Memory Organization and Interfacing. CSE 2312 Maher Al-Khaiyat. Semiconductor Memory. Capacity Kbits (Kilobits) Mbits (Megabits). Organization Number of locations => Number of address lines Size of a location => Number of data lines. Semiconductor Memory (cont’d). Speed Access time

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Memory Organization and Interfacing

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  1. Memory Organization and Interfacing CSE 2312 Maher Al-Khaiyat

  2. Semiconductor Memory • Capacity • Kbits (Kilobits) • Mbits (Megabits) • Organization • Number of locations => Number of address lines • Size of a location => Number of data lines

  3. Semiconductor Memory (cont’d) • Speed • Access time • Volatility • Programmability

  4. Number of address lines Number of locations Number of data lines Memory Organization

  5. Nonvolatile Memory • Read-Only Memory (ROM) • Programming or Burning • PROM; one-time programmable • EPROM; erasable using UV radiation • EEPROM; electrically erasable • Flash ROM; erasable in a flash (fast time) • Mask ROM; mask technology

  6. Volatile Memory • Random Access Memory (RAM) • Types • Static RAM (SRAM) • does not require refreshing • up to four transistors per cell • Dynamic RAM (DRAM) • requires refreshing • one transistor (capacitor) per cell

  7. D7 D0 32Kx8 A0 A15 A16 A14 A17 CS A18 A19 WR OE MEMW MEMR Address Decoding A19 A0 … … … Range of addresses 08000h to 0FFFFh

  8. Conventional Memory • 640K of RAM FFFFFh ROM 256K C0000h BFFFFh VDR 128K A0000h • Conventional memory • MS-DOS OS • Utilities • Applications • Etc… 9FFFFh RAM 640K 004FFh BIOS temp data 003FFh Interrupt vector table 00000h

  9. BIOS Data Area

  10. 64K x 4 64K x 4 64K x 1 Bank 3 64K x 4 64K x 4 64K x 1 Bank 2 256K x 4 256K x 4 256K x 1 Bank 1 256K x 4 256K x 4 256K x 1 Bank 0 DRAM Memory Banks Example configuration of 640KB RAM

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