Command & Data Handling System (C&DH) Peter Harvey David Curtis David McGrogan

1. Command & Data Handling • System • (C&DH) • Peter Harvey • David Curtis • David McGrogan • Space Sciences Laboratory • University of California, Berkeley

2. C&DH Agenda • AGENDA Overview CPU Requirements CPU Hardware FSW Requirements FSW Functions FSW Development FSW Verification GSE Hardware GSE Software

3. Processor Board Combined LVPS/Logic Overview

4. Requirements

5. CPU Card Microchip dsPIC33 16-bit CPU 2 SPI channels 2 UARTs 2 I2C channels 2 ECAN channels (can’t really use these) 10s of other pins (timers, ADCs, etc) Features Watchdog timer Brown-out reset Power-saving modes Language Support C Compiler, simulator, other items are free SALVO Real-Time Operating System

6. SPI

7. Direct Memory Access (DMA) STEIN COMM 2KB

8. PIC – MHX2400 (UART) PIC – EPS ( I2C ) PIC – SD card (SPI) PIC – FPGA (SPI) Data Paths SD CARD FPGA – Tx (bitsteam) FPGA – STEIN (SPI) FPGA – MAGIC (SPI) Additional Possibilities: PIC – MAGIC via software SPI • Peak Data Flow • Tx : 1 Mbps continuous • SDCARD : 1 Mbps average (including RTOS) • STEIN: 16 bits/event, 80KHz events = 1.28Mbps • MAGIC: 19 bits x 200 Hz x 3 axes = .011 Mbps • MHX2400: 0.080 Mbps

9. FSW Requirements

10. FSW Requirements

11. Design • FSW Major Modules

12. Boot/Initialization • Hardware Reset • Power-On • Watchdog Reset • Ground Command • Reset Sequence • Initializes Local Data RAM to zero • Issues Initialization Calls to Each Module • Starts in Safe Mode (low power) • Begins Engineering Telemetry (1-sec) • Checksums Uplinked programs • Selects first-program with Good Checksum • Waits Until 10 seconds elapsed time • Runs Selected Program

13. Modes & Enables • FSW Modes • Safe – Minimal Power Configuration, Resets to Safe, HV off • ACS – STEIN & S-Band off, Used to control attitude • Science - SDCARD Allowed, STEIN, S-Band Allowed, Actuators Disabled • Engineering - Actuators Allowed • Enable Mask Table Used to Maintain Power Balance

14. Timing • Interrupts • 1024 Hz Interrupt Process • Distributes CPU Time per Table • Basic table repeats 16Hz • CMD gets 32 Hz • TX gets 256 Hz • STEIN gets 512 Hz • MAG sample gets 128 Hz • Attenuator Control gets 16 Hz

15. Actuations • Actuators • Actuator Enable Must be Commanded On • MAG Boom Released by .25 to .50 second pulse to unit • STEIN Attenuator • Moving In / Out Controlled by FSW using STEIN count rates • Damage to Attenuator if commanded to reverse direction too soon • FSW automatic lockout for 240 (commandable) seconds after actuation

16. Development • FSW Development • Pumpkin Development Board • GSE Laptop running GSEOS • FSW Developed in phases • Verification Matrix Provides Status of Requirements • Comprehensive Performance Test on Development Board • Load into Flight System • Joins CINEMA Test Flow and Quality reporting • FSW Maintenance • Development Board Maintained in Flight-like Configuration • Verify command uploads prior to uplink • Anomaly resolution

17. Verification • FSW Verification • RBSP_EFW_FSW_002_Tables.xls tracks requirement flows • Development status, test overview and procedure name

18. GSE Requirements Sample Display (RBSP EFW)

19. GSEOS Sample Sample Display (RBSP EFW)

20. ISSUES • CPU • Floating Point Mult/Div/Add performance#’s needed • Memory Allocations (especially 2K DMA area) • FSW • Demonstrate SDCARD Simultaneous Store/Readback using RTOS (measure data rates) • Understand resources consumed by RTOS and C • Understand how RTOS and ACS-code will work • GSE • High Cost of RF test equipment