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Memory Modeling

Memory Modeling. مدل ساده. package body Mem_Pkg is constant DataWidth_c : Natural := 8; constant AddrWidth_c : Natural := 16; constant MaxDepth_c : Natural := 2 ** AddrWidth_c; -- 64K end Mem_Pkg; … entity Memory_Nty is

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Memory Modeling

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  1. Memory Modeling مرتضي صاحب الزماني

  2. مدل ساده package body Mem_Pkg is constant DataWidth_c : Natural := 8; constant AddrWidth_c : Natural := 16; constant MaxDepth_c : Natural := 2 ** AddrWidth_c; -- 64K end Mem_Pkg; … entity Memory_Nty is generic (FileName_g : String(1 to 12):= "memdata_.txt"); port( MemAddr : in Natural; MemData : inout Std_Logic_Vector(Mem_Pkg.DataWidth_c - 1 downto 0); RdWrF : in Std_Logic; CeF : in Std_Logic); -- Chip Select end Memory_Nty; مرتضي صاحب الزماني

  3. مدل ساده architecture Memory_a of Memory_Nty is begin -- Memory_a Memory_Lbl : process(MemAddr, MemData, RdWrF, CeF) subtype Data_Typ is Std_Logic_Vector(Mem_Pkg.DataWidth_c - 1 downto 0); subtype MemSize_Typ is integer range 0 to Mem_Pkg.MaxDepth_c - 1; type Mem_Typ is array(MemSize_Typ) of Data_Typ; variable Memory_v : Mem_Typ; begin … end; • اشکالات: حافظه ي زياد و زمان شبيه سازي بالا. مرتضي صاحب الزماني

  4. مدل کارآ تر • فقط براي I/O از std_logic_vector استفاده شود و براي داخل حافظه آرايه ي INTEGERبه کاررود. ( براي std_logic معمولا به ازاي هر عنصر، يک بايت گرفته مي شود). • به توابع تبديل type نياز داريم. • مقادير metalogical از دست مي روند. • عناصر حافظه را مي توان VARIABLE گرفت چون SIGNAL زمان و حافظه ي زيادي مصرف مي کند. ( فقط interfaceهاي حافظه از نوع سيگنال باشند). مرتضي صاحب الزماني

  5. Addr (0) data Addr (1) data Addr (255) data مدل Fixed Array Caching • معمولا براي شبيه سازي به تعداد محدودي از عناصر حافظه دسترسي مي يابيم (نه مثلا کل 4GB). •  از يک آرايه به سايز مثلا 256 استفاده مي کنيم ( به طولي که انتظار داريم کاربر به آن تعداد دسترسي خواهد يافت). • به يک متغير نياز داريم که نشان دهد تا کجا نوشته ايم (max). •  با هر دسترسي به حافظه در فيلد آدرسها جستجو مي کنيم. • براي نوشتن: به محض يافتن آدرس مورد تقاضا، داده را در آن انديس مي نويسيم. اگر اين آدرس قبلا موجود نبود آن را در آدرس ++max مي نويسيم. • براي خواندن: اگر اين آدرس قبلا موجود نبود “XXX..X” را روي خط data قرار مي دهيم. مرتضي صاحب الزماني

  6. مدل Fixed Array Caching entity RAM is generic(DataWidth_g : positive := 16; AddrWidth_g : positive := 32); port(Address : in Std_Logic_Vector(AddrWidth_g -1 downto 0); Data : inout Std_Logic_Vector(DataWidth_g -1 downto 0); CeF : in Std_Logic; RdWrF : in Std_Logic); end RAM; architecture RAMFIX_A of RAM is constant CacheSize_c : positive := 255; subtype CacheRange_Typ is integer range 0 to CacheSize_c; type CacheBlock_Typ is record Address: std_logic_vector (AddrWidth_g - 1 downto 0); Data : std_logic_vector (DataWidth_g - 1 downto 0); end record; begin مرتضي صاحب الزماني

  7. مدل Fixed Array Caching Mem_Lbl: process(Address, Data, RdWrF, CeF) type RAM_Typ is array (CacheRange_Typ) of CacheBlock_Typ; variable IndexMax_v : CacheRange_Typ := 0; variable RAM_v : RAM_Typ := (others => (Address => (others => 'X'), Data => (others => 'X'))); variable FoundAddr_v : Boolean; مرتضي صاحب الزماني

  8. مدل Fixed Array Caching begin if (CeF = '0') or (CeF = 'L') then FoundAddr_v := False; Search_Lbl: for Cache_i in 0 to IndexMax_v loop if RAM_v(Cache_i).Address = Address then -- Already accessed FoundAddr_v := True; if RdWrF'event and -- check for rising edge for a write ((RdWrF = '1') or (RdWrF = 'H')) and ((RdWrF'last_value = '0') or (RdWrF'last_value = 'L')) then RAM_v(Cache_i).Address := Address; RAM_v(Cache_i).Data := Data; elsif ((RdWrF = '1') or (RdWrF = 'H')) then Data <= RAM_v(Cache_i).Data; elsif RdWrF'event and -- check for falling edge for a write ((RdWrF = '0') or (RdWrF = 'L')) and ((RdWrF'last_value = '1') or (RdWrF'last_value = 'H')) then null; مرتضي صاحب الزماني

  9. مدل Fixed Array Caching else assert false report "Error in RdWrF signal" severity Warning; end if; exit Search_Lbl; end if; end loop; مرتضي صاحب الزماني

  10. مدل Fixed Array Caching if not FoundAddr_v then if RdWrF'event and -- check for rising edge for a write ((RdWrF = '1') or (RdWrF = 'H')) and ((RdWrF'last_value = '0') or (RdWrF'last_value = 'L')) then RAM_v(IndexMax_v).Address := Address; RAM_v(IndexMax_v).Data := Data; if IndexMax_v /= CacheSize_c then IndexMax_v := IndexMax_v + 1; else assert false report "Maximum limit for cache entry is reached" severity note; end if; مرتضي صاحب الزماني

  11. مدل Fixed Array Caching elsif ((RdWrF = '1') or (RdWrF = 'H')) then Data <= (others => 'X'); elsif RdWrF'event and -- check for falling edge for a write ((RdWrF = '0') or (RdWrF = 'L')) and ((RdWrF'last_value = '1') or (RdWrF'last_value = 'H')) then null; else assert false report "Error in RdWrF signal" severity Warning; end if; end if; else -- Ce_F /='0'| 'L' data <= (others => 'Z'); end if; end process Mem_Lbl; end RamFix_a; مرتضي صاحب الزماني

  12. مدل Fixed Page Caching • براي هر page address ، يک صفحه از RAM (و نه يک word ) در دسترس قرار مي گيرد. Addr Data ِData … Data (0) Addr Data ِData … Data (255) مرتضي صاحب الزماني

  13. مدل Dynamic Page Caching • مانند Fixed Page اما به صورت ليست پيوندي. مرتضي صاحب الزماني

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