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Dell may have shipped infected motherboards 

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control 2010-07-22. Instructor Paul Pearce. Dell may have shipped infected motherboards .

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Dell may have shipped infected motherboards 

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  1. inst.eecs.berkeley.edu/~cs61cCS61C : Machine StructuresLecture 19CPU Design: The Single-Cycle II & Control2010-07-22 Instructor Paul Pearce Dell may have shipped infected motherboards Dell is warning customers that its PowerEdge R410 rack-mount server may have shipped with spyware onboard in the embedded system management software (firmware). Good luck getting Norton McAfee to clean that. http://www.theregister.co.uk/2010/07/21/dell_server_warning/

  2. How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements • meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

  3. Clocking Methodology Clk • Storage elements clocked by same edge • Being physical devices, flip-flops (FF) and combinational logic have some delays • Gates: delay from input change to output change • Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay • “Critical path” (longest path through logic) determines length of clock period . . . . . . . . . . . .

  4. ALU Register-Register Timing: One complete cycle Clk PC New Value Old Value Instruction Memory Access Time Rs, Rt, Rd, etc Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr New Value Old Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value ALUctr RegWr Rd Rs Rt Register Write Occurs Here 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 clk

  5. op rs rt 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits ALU 3c: Logical Operations with Immediate • R[rt] = R[rs] op ZeroExt[imm16] 31 26 21 16 0 immediate 6 bits 5 bits 5 bits 16 bits But we’re writing to Rt register?? ALUctr RegWr Rd Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 clk

  6. op rs rt 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits ALU 3c: Logical Operations with Immediate • R[rt] = R[rs] op ZeroExt[imm16] ] 31 26 21 16 0 immediate 6 bits 5 bits 5 bits 16 bits RegDst Rd Rt What about Rt register read?? 1 0 RegWr Rs Rt ALUctr 5 5 5 busA 32 Rw Ra Rb 32 RegFile busB 32 0 32 clk imm16 1 ZeroExt 16 32 ALUSrc • Already defined 32-bit MUX; Zero Ext?

  7. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits ALU 3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 RegDst Rd Rt 1 0 RegWr Rs Rt ALUctr 5 5 5 busA 32 Rw Ra Rb 32 RegFile busB 32 0 32 clk imm16 1 ZeroExt 16 32 ALUSrc

  8. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk ? 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  9. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  10. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 1 0 ALU 0 1 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  11. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction beq rs, rt, imm16 • mem[PC] Fetch the instruction from memory • Zero = R[rs] - R[rt] Calculate branch condition • if (Zero) Calculate the next instruction’s address • PC = PC + 4 + ( SignExt(imm16) x 4 ) else • PC = PC + 4

  12. Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (zero) 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 00 PC Inst Address Zero nPC_sel 4 ALUctr RegWr Rs Rt Adder 5 5 5 busA 32 z Rw Ra Rb busW 32 Mux RegFile ALU busB Adder 32 clk clk PC Ext Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16

  13. Putting it All Together:A Single Cycle Datapath Inst Memory Adr Adder Adder Mux 1 0 z 00 ALU 0 PC 0 WrEn Adr 1 1 Extender Data Memory PC Ext Instruction<31:0> <0:15> <21:25> <16:20> <11:15> Rs Rt Rd Imm16 RegDst nPC_sel MemtoReg ALUctr Rd Rt Zero MemWr RegWr Rs Rt 4 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 clk imm16 Data In 16 32 clk imm16 ExtOp ALUSrc

  14. ALU An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Addr Data Out Rw Ra Rb 32 32 Ideal Data Memory 32 Register File PC Next Address B Data In clk clk clk 32 Datapath

  15. ALU An Abstract View of the Critical Path Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write Ideal Instruction Memory Instruction (Assumes a fast controller) Rd Rs Rt 5 5 5 Instruction Address A Data Addr Rw Ra Rb 32 32 Ideal Data Memory 32 Register File PC Next Address B Data In clk clk clk 32

  16. Administrivia • HW 7 due Saturday • Specification update now online. Be sure to check it out. The changes are designed to make integration with project 2 easier. They are very minor. • Project 2 online now! • Reminder: Midterm regrades due Monday. • Paul will be gone on Monday. Noah will be giving the lecture. • Paul will have OH on Monday (barring flight delays) • Be prepared for a kinetic learning activity

  17. Instruction<31:0> instr fetch unit nPC_sel <0:15> <21:25> <16:20> <11:15> clk Rs Rt Rd Imm16 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory Review: A Single Cycle Datapath • We have everything but the values of control signals RegDst Rd Rt ALUctr MemtoReg RegWr Rs Rt zero MemWr 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ExtOp ALUSrc

  18. 00 PC Recap: Meaning of the Control Signals • nPC_sel: “+4” 0  PC <– PC + 4 “br” 1  PC <– PC + 4 + {SignExt(Im16) , 00 } • Later in lecture: higher-level connection between mux and branch condition “n”=next Inst Address nPC_sel 4 Adder 0 Mux 1 Adder clk PC Ext imm16

  19. 1 0 ALU 0 1 Recap: Meaning of the Control Signals • MemWr: 1  write memory • MemtoReg: 0  alu; 1  mem • RegDst: 0  rt; 1  rd • RegWr: 1  write register • ExtOp: zero, sign • ALUsrc: 0  reg; 1  imm • ALUctr:ADD, SUB, OR MemtoReg ALUctr RegDst Rd Rt MemWr RegWr Rs Rt 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 0 32 clk 32 WrEn Adr imm16 Data In 1 Extender Data Memory 16 32 clk ALUSrc ExtOp

  20. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL: The Add Instruction add rd, rs, rt • MEM[PC] Fetch the instruction from memory • R[rd] = R[rs] + R[rt] The actual operation • PC = PC + 4 Calculate the next instruction’s address

  21. 00 PC Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] • same for all instructions Inst Memory Instruction<31:0> nPC_sel Inst Address 4 Adder Mux Adder clk PC Ext imm16

  22. 31 26 21 16 11 6 0 op rs rt rd shamt funct 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] Instruction<31:0> instr fetch unit nPC_sel=+4 RegDst=rd <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=ADD zero RegWr=1 Rs Rt MemtoReg=ALU 5 5 5 MemWr=0 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=reg ExtOp=x

  23. 00 PC Instruction Fetch Unit at the End of Add • PC = PC + 4 • This is the same for all instructions except: Branch and Jump Inst Memory nPC_sel=+4 Inst Address 4 Adder Mux Adder clk PC Ext imm16

  24. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory Single Cycle Datapath during Or Immediate? • R[rt] = R[rs] OR ZeroExt[Imm16] Instruction<31:0> instr fetch unit nPC_sel= RegDst= <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr= zero RegWr= Rs Rt MemtoReg= 5 5 5 MemWr= busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc= ExtOp=

  25. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory Single Cycle Datapath during Or Immediate? • R[rt] = R[rs] OR ZeroExt[Imm16] Instruction<31:0> instr fetch unit nPC_sel=+4 RegDst=rt <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=OR zero RegWr=1 Rs Rt MemtoReg=alu 5 5 5 MemWr=0 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=imm ExtOp=zero

  26. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Load? • R[rt] = Data Memory {R[rs] + SignExt[imm16]} Instruction<31:0> instr fetch unit nPC_sel= RegDst= <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr= zero RegWr= Rs Rt MemtoReg= 5 5 5 MemWr= busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc= ExtOp=

  27. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Load • R[rt] = Data Memory {R[rs] + SignExt[imm16]} Instruction<31:0> instr fetch unit nPC_sel=+4 RegDst=rt <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=ADD zero RegWr=1 Rs Rt MemtoReg=mem 5 5 5 MemWr=0 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=imm ExtOp=sign

  28. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Store? • Data Memory {R[rs] + SignExt[imm16]} = R[rt] Instruction<31:0> instr fetch unit nPC_sel= RegDst= <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr= zero RegWr= Rs Rt MemtoReg= 5 5 5 MemWr= busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc= ExtOp=

  29. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Store • Data Memory {R[rs] + SignExt[imm16]} = R[rt] Instruction<31:0> instr fetch unit nPC_sel=+4 RegDst=x <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=ADD zero RegWr=0 Rs Rt MemtoReg=x 5 5 5 MemWr=1 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=imm ExtOp=sign

  30. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Branch? • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31:0> instr fetch unit nPC_sel= RegDst= <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr= zero RegWr= Rs Rt MemtoReg= 5 5 5 MemWr= busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc= ExtOp=

  31. 31 26 21 16 0 op rs rt immediate 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory The Single Cycle Datapath during Branch • if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 Instruction<31:0> instr fetch unit nPC_sel=br RegDst=x <0:15> <21:25> <16:20> <11:15> clk Rd Rt Rs Rt Rd Imm16 ALUctr=SUB zero RegWr=0 Rs Rt MemtoReg=x 5 5 5 MemWr=0 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ALUSrc=reg ExtOp=x

  32. 31 26 21 16 0 op rs rt immediate Inst Memory Adr MUX ctrl 00 PC Q: What logic gate? Instruction Fetch Unit at the End of Branch • if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Instruction<31:0> nPC_sel • What is encoding of nPC_sel? • Direct MUX select? • Branch inst. / not branch • Let’s pick 2nd option • nPC_sel = +4  0 • nPC_sel = br  1 Zero nPC_sel 4 Adder 0 Mux 1 Adder imm16 clk PC Ext

  33. Peer Instruction In the worst case, the biggest delay is the memory access time With only changes to control, our datapath could write (something) to memory and registers in one cycle. 12 a) FF b) FT c) TF d) TT

  34. Peer Instruction Answer Memory has by far a higher access time than combinational logic. TRUE Let’s look back at the datapath. Take a sw instructions. Can we also write to a register? If so, which reg? What value? TRUE In the worst case, the biggest delay is the memory access time With only changes to control, our datapath could write (something) to memory and registers in one cycle. 12 a) FF b) FT c) TF d) TT

  35. Instruction<31:0> instr fetch unit nPC_sel <0:15> <21:25> <16:20> <11:15> clk Rs Rt Rd Imm16 1 0 Z ALU 0 0 WrEn Adr 1 1 Extender Data Memory Summary: A Single Cycle Datapath • We have everything! Now we just need to know how to BUILD CONTROL RegDst Rd Rt ALUctr MemtoReg RegWr Rs Rt zero MemWr 5 5 5 busA 32 Rw Ra Rb busW 32 RegFile busB 32 32 clk 32 imm16 Data In 16 32 clk ExtOp ALUSrc

  36. Summary: Single-cycle Processor • 5 steps to design a processor • 1. Analyze instruction set  datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Formulate Logic Equations • Design Circuits Processor Input Control Memory Datapath Output

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