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Approach: Using difference between non-ideal (expt.) and ideal (simulated)

Trap density metrology in state of art Si n- finFETs – A. Paul, G. Tettamanzi , S. Lee, S. Mehrotra , S. Rogge & G. Klimeck. Approach: Using difference between non-ideal (expt.) and ideal (simulated) Source to channel barrier height ( E b ) Active channel area (S).

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Approach: Using difference between non-ideal (expt.) and ideal (simulated)

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  1. Trap density metrology in state of art Si n-finFETs– A. Paul, G. Tettamanzi, S. Lee, S. Mehrotra, S. Rogge & G. Klimeck Approach: Using difference between non-ideal (expt.) and ideal (simulated) • Source to channel barrier height (Eb) • Active channel area (S). • For trap density (Dit) estimation in [100]/ [110], Si nfinFETs. Objective: Direct trap density estimation in actual Si <100>/<110> n-finFETs. Adv: No special Structure needed N-finFET TEM image • Typical Ditin 1-10 xe11/cm2range • <110> FETs ~2X more • Dit than <100> due to more • surface bonds. • Higher Dit in thinner nFETs (H=65,W=5nm). • More Dit in 3D FETs compared to planar FETs. • H2 passivation ~1.5X reduction in Dit.. Results : Dit estimation in two n-finFETs . Work published in IEEE, EDL. (DOI: 10.1109/LED.2011.2106150)

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