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ROC Design Issues

ROC Design Issues. Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay & Mr. Suman Sau. Basic Read Out System Interfacing With Analog Signal using SPI RS 232 Serial Communication Communication With TEMAC Ethernet Core Conclusion. Outline. Any PC Connectivity. ETH PHY.

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ROC Design Issues

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  1. ROC Design Issues Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay & Mr. Suman Sau CBM

  2. Basic Read Out System Interfacing With Analog Signal using SPI RS 232 Serial Communication Communication With TEMAC Ethernet Core Conclusion Outline CBM

  3. Any PCConnectivity ETH PHY Basic Readout System Front-End Board Read-OutController Detector FEEB ROC Detector Tag data XYTER ADC data FPGA ADC XYTER Tag data control clock cableconnection 2 N-XYTER256 ch. LVDS signalcable

  4. Interfacing With Analog Signal

  5. Serial Peripheral Interface Bus • The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. • The SPI bus specifies four logic signals. • SCLK — Serial Clock (output from master) • MOSI/SIMO — Master Output, Slave Input (output from master) • MISO/SOMI — Master Input, Slave Output (output from slave) • SS — Slave Select (active low; output from master) SCLK SPI Master MOSI MISO --- SS SCLK SPI MOSI Slave MISO --- SS CBM

  6. Analog Capture Circuit in SPARTAN 3E

  7. Results Figure shows the digital values corresponding to the onboard analog voltage according to equation

  8. Analog module interfacing with FPGA PmodAD1 Analog I/P (Audio Signal) 12-bit Digital Value Spartan 3E FPGA PmodDA2 PmodDA2 12-bit Digital Value I/P for D/A converter Analog O/P SPI Bus Communication has been successfully established CBM

  9. Real Time Digital Conversion of audio signal Top view of the implemented architecture

  10. Testing of the Audio Communication

  11. Analog module interfacing with FPGA Virtex-4LX/SX Development Board P160 Analog Module CBM

  12. Problem Regarding P160& Virtex-4LX/SX • Analog Module P160 is not physically adjustable with Virtex-4 LX/SX • We need P240 Analog Module which is physically compatible. • Order to buy P240 Analog Module already Placed CBM

  13. RS 232 Communication

  14. Communication through RS232 Ciphertext Send and Receive Real Time Data From Key Board RS232_DCE RS232_DTE RSA 32 bit Crypto core Downloading LED Display Bit File Spartan 3E Board CBM

  15. RSA Engine for Real Time Communication

  16. Communication through RS232 with PC CBM

  17. Loop back Communication through RS232

  18. Communication with TEMAC Ethernet Core on ML505

  19. TEMAC (Loop Back) Testing in ML505 P H Y EMAC TEMAC Ethernet FIFO TX Client FIFO Address Swap Module RX Client FIFO It is a simple design that mirrors incoming Ethernet packets CBM

  20. Status of the Ethernet Communication before running of the program Status of the Ethernet Communication after the program was run CBM

  21. Conclusion • Research team at C.U, can contribute in the CBM research: • Development of Firmware for ROC boards. • Testing of the ROC board with the  Firmware to be supplied by GSI. • Board level testing  of the ROC provided we can get funding for the manpower and testing equipments for board level testing. • Developmental activities for circuit design and process technology based research for the ASIC design, again we require some funding for this to procure the IC design tools. • Research for radiation hardened FPGA development.

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