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A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture. Manuscript received August 25, 2006; revised December 3, 2006. This work was jointly supported by the grant HKUST 6288/04E funded by the Research Grant Council,

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A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

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  1. A 1-V 100-MS/s 8-bit CMOS Switched-OpampPipelined ADC Using Loading-Free Architecture Manuscript received August 25, 2006; revised December 3, 2006. This work was jointly supported by the grant HKUST 6288/04E funded by the Research Grant Council, HongKong, and the project ITS/033/02 funded by the Innovation and Technology Fund, Hong Kong. P. Y. Wu and H. C. Luong are with the Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong (e-mail: patwu@ust.hk). V. S.-L. Cheung is with Pericom Technology Incorporated, Hong Kong. Digital Object Identifier 10.1109/JSSC.2007.891666 Patrick Y. Wu, Vincent Sin-Luen Cheung, and Howard C. Luong, Senior Member, IEEE 指導教授：易昶霈 學　　生：吳柏翰 　學　　號：97662002

  2. Outline • Introduction • Architecture • Measurement Results • Conclusion

  3. Introduction

  4. Architecture

  5. Architecture

  6. Architecture

  7. Architecture

  8. Architecture

  9. Measurement Results

  10. Measurement Results

  11. Measurement Results

  12. Measurement Results

  13. Conclusion

  14. Thank you for your attention.

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