Local Merges for Effective Redundancy in Clock Networks

1. Local Merges for Effective Redundancy in Clock Networks Rickard Ewetz and Cheng-KokKoh School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-2035

2. Outline • Introduction • Problem Definition • Case Study • The Proposed Methodology • Experimental Results • Conclusions

3. Introduction • The synthesis of clock networks is an important design step of modern ICs. • A clock network delivers a synchronizing signal to all sequential elements in a synchronized circuit to trigger them almost simultaneously. • Clock skew is the difference of the arrival times between a pair of sequential elements

4. Introduction • Process and environmental variations affect the reliability of clock networks. • By synthesizing non-tree structures, the robustness of clock networks can be improved at the expense of higher capacitance. • Cross links • Meshes • Multilevel fusion trees

5. Introduction • Non-tree clock network structures Cross Link Clock Mesh • Multilevel fusion trees

6. Problem Definition • Construct a clock network given: • Inverter/wire library, blockages, sink locations and loads. • Process variation model (supply voltage/wire width) • ISPD 2010 contest model (ISPD) • Single Location Single Voltage (SLSV) • Objective: • Minimize Capacitance • Constraints: • 95% Local skew • Slew • No inverters placed within blockages

7. Process variation model • ISPD 2010 contest model (ISPD) • Single Location Single Voltage (SLSV)

8. Case Study • Inserting any cross link improves the robustness compared to the original tree structure. • As the cross link is placed closer to the sinks the skew is successively reduced.

9. Case Study • The capacitance distribution over stages of a clock tree constructed on benchmark circuit ispd10cns01

10. The Proposed Methodology • Redundancy introduced in the bottom stage is more effective in improving the robustness. • The bulk of the capacitance of a clock network is at the bottom • A trade off between cost and robustness by introducing the redundancy in the second bottom-most stage

11. The Proposed Methodology

12. Normal Stage Merging • Deferred-Merge Embedding (DME) • Topology generation by merging two nodes with • Physically close to each other (NNG) • Equal nominal delay [12] • If driving the newly merged subtreewith max buffer violates the slew constraint, the two subtrees are unmerged and locked.

13. Deferred-Merge Embedding (DME)

14. Stage 2 Multiple Local Merges • Sequential relation graph (SRG).

15. Stage 2 Sparsification • To ensure a unique path from the driving device of the subtree to each subtreeif no slew violation.

16. Experimental Results • Implemented in C++ • Run on a quad core 3.1GHz Linux machine with 7.7GB memory • ISPD 2010 Benchmark suit for both the ISPD variations model and the SLSV variations model.

17. Comparisons of 95% skew and cost under the ISPD model

18. Comparisons of 95% skew and cost under the SLSV model

19. Experimental Results • ISPD • 1 % lower capacitance on average. • Significantly lower skew. • SLSV • 22% lower capacitance on average. • Satisfies BM01 and BM02 with 3x lower cap. • No sparsification on BM03 to meet skew constraint.

20. Comparison with multilevel fusion trees on BM08

21. Conclusions • Analyze the effectiveness of redundant paths in reducing the effects of variations • Propose a CNS technique that introduces redundant paths close to the clock sinks by performing multiple local merges. • Evaluation performed under the ISPD and SLSV models shows that with modest overhead in capacitance, our proposed solutions can improve robustness.