EMC of ICs Practical Trainings

1. EMC of ICsPractical Trainings

2. Objectives • Get familiar with IC-EMC/Winspice • Illustrate parasitic emission mechanisms • Understand parasitic emission reduction strategies • Power Decoupling Network modelling • Basis of conducted and radiated emission modelling • Basis of immunity modelling

3. Summary • IC-EMC – Reference • Basic concepts • Ex. 1. FFT of typical signals • Ex. 2. Transient current estimation • Ex. 3. Interconnect parasitics • Ex. 4. Impedance mismatch • Ex. 5. Crosstalk • Emission • Ex. 6. di/dt noise • Ex. 7. PDN modeling • Case study: Optimization of Starcore PCB (ICEM model)

4. IC-EMC - Simulation flow IC-EMC schematic Editor (.sch) IC-EMC model libraries WinSPICE compatible netlist generation (.cir) Measurement import WinSPICE simulation IC-EMC Post-processing tools (emission, impedance, S-parameters, immunity) Output file generation

5. IC-EMC – Most Important Icons

6. IC-EMC – Link to WinSpice • Click on WinSPICE.exe • Click File/Open to open a circuit netlist (.cir) generated by ic-emc. • IC-EMC main commands (text line):

7. Create the schematic Set the source generator Transient simulation FFT by IC-EMC Simulate the FFT of a sinus and a square signal Exercise 1. FFT of typical signals 7

8. Exercise 1. FFT of typical signals • FFT of a sinus source • Set the voltage generator properties: • Frequency = 1 GHz • Amplitude = 1 V Ex1-FFT-sinus.sch 8 8

9. Exercise 1. FFT of typical signals • FFT of a sinus source • Type the simulation command: .tran 1n 50n • Simulate the response in time domain. • Compute the FFT. • Does the FFT result correlate with theoretical result ?

10. Exercise 1. FFT of typical signals • FFT of a square current source • Set the generator properties • For example: • Period = 10 n, • PW = 4 n, • Tr = 1n, Tf = 1 n • V0 = 0 V, V1 = 1 V Ex1-FFT-Pulse.sch

11. Exercise 1. FFT of typical signals • FFT of a square source For a trapezoidal signal (Tr=Tf) For a square signal (Tr=0)

12. Exercise 2. Transient current estimation • Standard cell inverter in CMOS technology • Typical load capacitance • Observe in time domain the current through Vss. Ex2-transient_inverter.sch

13. Exercise 2. Transient current estimation • Time domain simulation • Adjust scales (Autofit and zoom on time axis)

14. Exercise 2. Transient current estimation • What is the influence of the load capacitance (1 fF to 1 pF) ? Rise time Ipeak Cload Cload

15. Exercise 3. Interconnect parasitics • The core is mounted in a QFP64 package. • A pair of pins is dedicated to supply the core 12 mm 6 mm 1.5 mm 25 µm 0.7 mm 3.5 mm 0.22 mm Evaluate the electrical parasitic associated to the power supply pair.

16. Exercise 3. Interconnect parasitics • Use Tools/Interconnects Parameters to evaluate R, L, C associated to package pins. • Empirical estimation : • Lead : L = 0.5 nH/mm and C = 0.1 pF/mm • Bonding : L = 1 nH/mm

17. Exercise 4. Impedance Mismatch Section of the line • Let’s consider the following link between 2 digital inverters. No matching is placed at each termination. • The digital inverters are 74AHCT04, from NXP. The IBIS file ahct04.ibs is given. • Build a SPICE model to evaluate the signal integrity at each termination of this digital link. Top layer (signal line + power) 35 µm W = 0.36 mm 1.6 mm FR4 (εr = 4.5) 35 µm Bottom layer – GND plane 5 V power supply + filtering 2nd inverter: input driver 1st inverter: output driver 1 MHz square signal 10 cm 120 Ωmicrostrip line

18. Exercise 4. Impedance Mismatch • From IBIS file, propose an equivalent model for input and output driver. • “File > Load IBIS” ahct04.ibs Package outline Input Output Functional diagram

19. Exercise 4. Impedance Mismatch Measured I(V) charac. Of output buffer • Proposed models for input and output driver. IBIS_buffer_out_carac_IV.sch Measured I(V) charac. Of input buffer IBIS_input_buffer_IV.Sch

20. Exercise 4. Impedance Mismatch • Verify the theoretical characteristic impedance of the microstrip line (“Tools > Interconnect Parameters”). • The following S11 measurements have been done: • Line open (zin-line120-open.s1p) • Line loaded by 51 Ω resistor (zin-line120-load51.s1p) • Line loaded by 120 Ω resistor (zin-line120-match.s1p) • Propose an equivalent model for the line. zin-line120-open.s1p zin-line120-match.s1p

21. Exercise 4. Impedance Mismatch Output driver • Build the complete electrical model of the digital link. • Simulate the transient response of signal at each termination of the link. • Validate your model from measurements: • Rising waveform at output driver (rw_out_no_match.tran) • Falling waveform at output driver (fw_out_no_match.tran) • Rising waveform at input driver (rw_in_no_match.tran) • Falling waveform at input driver (fw_in_no_match.tran) Input driver

22. Exercise 4. Impedance Mismatch Input driver – R matching • Two solutions are proposed to improve signal integrity: • Place two 120Ω resistors at both line terminals • Place one 120Ω resistor at output driver side, one 120Ω resistor and a serial 4.7 pF capacitor • Test the effect of both solutions. • Validate your models from measurements: • Rising waveform at output driver (rw_out_matchR.tran and rw_out_matchRC.tran) • Falling waveform at output driver (fw_out_matchR.tran and fw_out_matchRC.tran) • Rising waveform at input driver (rw_in_matchR.tran and rw_in_matchRC.tran) • Falling waveform at input driver (fw_in_matchR.tran and fw_in_matchRC.tran) Input driver – RC matching

23. Exercise 5. Crosstalk Section of the line • Let’s consider the following link between 2 digital inverters (74AHCT04). No matching is placed at each termination. • A second line loaded by 47 Ωat each terminals is placed at close distance (2W) • Build a SPICE model to evaluate the crosstalk at each termination of the victim line (near-end and far-end). Top layer (signal line + power) 2W 35 µm W = 1 mm W = 1 mm 1.6 mm FR4 (εr = 4.5) 35 µm Bottom layer – GND plane 5 V power supply + filtering 1st inverter: output driver 2nd inverter: input driver Aggressor line Victim line 1 MHz square signal 23 August 14

24. Exercise 5. Crosstalk Near end • Build the complete electrical model of the coupled lines. • Simulate the transient response of signal at each termination of the victim line. • Validate your model from measurements: • Near end crosstalk (NE_ctlk.tran) • Far end crosstalk (FE_ctlk.tran) Far end

25. Exercise 6. di/dt noise • Estimate the voltage bounce on Vdd and Vss pins of the core when it is mounted in a QFP 64. • The core clock is 20 MHz. Core noise margin ? Ex4-didt_noise.sch

26. Exercise 6. di/dt noise

27. Exercise 6. di/dt noise • Inductance evaluation Impedance vs. Freq z11-dspic-vdd_10-vss_9.z

28. Exercise 6. di/dt noise • What IBIS Says ? Typ min max R_pkg 19.05m 21.2m 16.9m L_pkg 3.025nH 2.61nH 3.44nH C_pkg 0.269pF 0.268pF 0.270pF

29. Exercise 7. PDN Modeling Impedance vs. Freq • DSPIC Z(f): find an R,L,C model • Tune to measurement file: z11-dspic-vdd_10-vss_9.z

30. Exercise 7. PDN Modeling Impedance vs. Freq z11-C1nF_0603.z 1nF discrete capacitance for DPI

31. Synthesis of Exercises 1 to 7 • What did we learn ?