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Interface Design PCB Design Tips. Omid Fatemi. Outline. IC Technology. TTL NMOS CMOS BiCMOS. IC Fan-Out. Fan-out (low) = . Example. Capacitance Derating. Capacitance of IC pins (5 to 7 pF) I = CVF Each 50 – 100 pF capacitor extra 3 ns delay. Example. Ground Bounce.
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Interface DesignPCB Design Tips Omid Fatemi
IC Technology • TTL • NMOS • CMOSBiCMOS
IC Fan-Out • Fan-out (low) =
Capacitance Derating • Capacitance of IC pins (5 to 7 pF) • I = CVF • Each 50 – 100 pF capacitor • extra 3 ns delay
Transient Current • I = C (dV/dt) • Change in V peak in I • Decoupling capacitormake less change in V • .01 - .1 microF between Vcc and Gnd
Cross-talk • More distance • Shorter • Ground lines between traces
High Speed Design • Between CPU and Cache • Short cycle and access time required • zero wait state • Timing analysis required • Assume: CPU 60MHz, access time: 10ns
Timing Analysis • tflight = tclock skew + tpropagation delay + trise time • Clock skew: • Difference in rising and falling edge of clock cycle for different components • Propagation delay • RC analysis • Transmission line analysis • Rise time • Speed of component driving the line • External capacitive loading should be considered
Problems • 4, 5, 21, 37 • 40, 42