VHDL Simulation & Synthesis Data Types

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VHDL Simulation & Synthesis Data object

Agenda • Data Type • Data Properties • Data Object • Operation

Agenda • Data Type • Integer Type • Physical Type • Floating Point Type • Enumeration Type • Arrays • Recorders • Subtypes • Data Properties • Data Object • Operation

Integer Type • Definition • TypeIntTypeNameisrangeInt1toInt2 (Int1 and Int2 are integers and Int1 < Int2) • TypeIntTypeNameisrangeInt1downtoInt2 (Int1 and Int2 are integers and Int1 > Int2)

Integer Type Example • Example • Typebyte_intisrange0to255 • Typesigned_byteisrange-128to127; • TypeBit_idxisrange7downto0; • Pre-defined type (standard.vhd) TYPE INTEGER IS RANGE -2147483648 TO 2147483647;

Integer Signal Example signal a: integer; … a <= 1; --  a <= -1; --  a <= 1.0; --  a <= 1 ns; -- 

Physical Type • Definition typeNewNameis rangeInt1toInt2 unitsUnitName1; UnitName2 = ???UnitName1; UnitName3 = ??? UnitName2; UnitName4 = ??? UnitName3; ... ; end units[NewName];

Physical Type Example (Time) TYPETIMEISRANGE-9223372036854775808TO9223372036854775807 UNITSfs; ps = 1000fs; ns = 1000ps; us = 1000ns; ms = 1000us; sec = 1000ms; min = 60sec; hr = 60min; END UNITS; Note 2.5 ps -- = 2500 fs  2.50001ps -- = 2500.1 fs 

Physical Type Example (Resistance) typeresistanceis range0to1E8 units ohms; kohms = 1000 ohms; Mohms = 1E6ohms; end units;

Physical Type (Package) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; packagemy_package is constant const_K : integer := 100; type state_type is (idle, s0, s1, s2, s3); subtype Byte is Std_logic_vector(7 downto 0); typeCurrentis range0to1000000000 unitsnA; uA = 1000nA; mA = 1000uA; A = 1000mA; end units; endmy_package;

Physical Type (Utype.vhd) library ieee, work; use ieee.std_logic_1164.all; use work.my_package.all; entity UType is port(out_current : out current; control : in std_logic_vector(1 downto 0)); end UType; architectureUType_arch of UType is begin out_current <=1 uAwhen control = "00" else 10uAwhen (control = "01") else 100uAwhen (control = "10") else 10mA; -- 1500 mA is not allowed since it -- is out of unit range (0 to -- 1000,000,000nA) end UType_arch;

Floating Point Type • Definition • TypeRealTypeNameisrangeRel1toRel2 (Rel1 and Rel2 are real numbers and Rel1 < Rel2) • Pre-defined type in standard.vhd TYPE REAL IS RANGE -1.7014110e+038 TO 1.7014110e+038;

Floating Type Example • typesignal_levelis range-10.00to+10.00; • typeprobabilityis range0.0to1.0; • Note: VHDL find floating point type by decimal point!

Floating Type use variable b: real; … b := 1.0; --  b := 1; -- 

Enumeration Types • Definition typeTypeNameis (Item_1, Item_2, …, Item_N);

Enumeration Example (standard.vhd) • TYPEBOOLEANIS (FALSE, TRUE); • TYPEBITIS('0', '1'); • TYPECHARACTERIS ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', DEL);

Enumeration Type Example typeCOLORis(Red, Orange, Yellow, Green, Blue, Indigo, Violet); typeSTATEis(S0, S1, S2, S3); ... ... signal COLOR_S :COLOR; signal STATE_S :STATE; ... ... COLOR_S<= Blue; STATE_S<= S2;

Arrays • Definition • typeNewNameis array(IndexTypeName range <>, ...)ofDataType; • typeNewNameis array( Range, ...)ofDataType;

Array Example (Def1) • typeNewNameis array(IndexTypeName range <>, ...)ofDataType; • TYPEstd_logic_vectorIS ARRAY( NATURAL RANGE <>)OFstd_logic; • typevectoris array(integer range <>)of real;

Array Example (Def2) • typeNewNameis array( Range, ...)ofDataType; • typeBit_8is array(7 downto 0)of bit; • typeBit_4x8is array(0 to 3)of Bit_8; • type Bit_4_8is array(0 to 3, 7 downto 0)of bit;

signal COLOR_S : COLOR; signal STATE_S : STATE; signal Byte : Bit_8; signal Color_Table : COLOR_ARRAY(0 to 3); signal Color_Number : COLOR_COUNT(Orange to Indigo); ... Byte <= "10100011"; Color_Table(0) <= Green; Color_Table(1) <= Violet; Color_Table(2) <= Red; Color_Table(3) <= Blue; Color_Number(Green) <= 2; Color_Number(Orange) <= 75; ... variable Bit_s : bit; ... Bit_s := Byte_Table1(3)(2); -- '1' Bit_s := Byte_Table2(3, 2); -- '1‘ Array Example typeCOLOR is (Red, Orange, Yellow, Green, Blue, Indigo, Violet); typeBit_8isarray(7 downto 0)ofbit; typeBit_4x8isarray(0 to 3) of Bit_8; typeBit_4_8isarray(0 to 3, 7 downto 0)ofbit; typeCOLOR_ARRAYisarray(natural range<>) of COLOR; typeCOLOR_COUNTis array(COLOR range<>)ofinteger; constant Byte_Table1 : Bit_4x8 := ( ('1', '0', '1', '1', '0', '0', '0', '1'), ('0', '0', '0', '1', '1', '0', '1', '1'), ('0', '1', '0', '0', '0', '1', '0', '0'), ('1', '0', '0', '0', '1', '1', '0', '1') ); constant Byte_Table2 : Bit_4_8 := ( ('1', '0', '1', '1', '0', '0', '0', '1'), ('0', '0', '0', '1', '1', '0', '1', '1'), ('0', '1', '0', '0', '0', '1', '0', '0'), ('1', '0', '0', '0', '1', '1', '0', '1') );

Records • Definition • typeNewNameis record ElementName, ElementName,... :DataType1; ElementName, ElementName,... :DataType2; ... ; end record[NewName];

Records Example typeInfo_Recordis record Dat0 :integer; Dat1 :Bit_8; end record; ... Signal Info : Info_Record; ... Info.dat0<= 10; Info.dat1(4)<= '0';

Subtypes • Definition • subtypeSubTypeName is TypeName range (RANGE);

Subtype Example typeINT_LARGEis range 100 to1000; subtypeINT_SMALL_AisINT_LARGErange150 to 200; subtypeINT_SMALL_BisINT_LARGErange100 to 1000; subtypeINT_SMALL_C isINT_LARGE; ... ... variable i : INT_LARGE; variable ia : INT_SMALL_A; variable ib : INT_SMALL_B; variable ic : INT_SMALL_C; ... ... i := 500; --  ia := 150; --  ib := 300; --  i := ia; --  ia := ib; -- ? ia := i; -- ? ic := 700; -- 

Agenda • Data Type • Data Properties • Data Object • Operation

Data Properties T'BASE The base type of T. Only allowed as prefix to another attribute T'LEFT Left bound of T T'RIGHT Right bound of T T'LOW Lower bound of T T'HIGH Upper bound of T T'POS(X) Position number of X in T T'VAL(X) Value with position number X in T T'SUCC(X) Successor = T'VAL(T'POS(X)+1) T'PRED(X) Predecessor = T'VAL(T'POS(X)-1) T'LEFTOF(X) Value to the left of X in T T'RIGHTOF(X) Value to the right of X in T

Data Properties Example (1) type T is (A, B, C, D, E); subtype S is T range D downto B; S'LEFT = D S'RIGHT = B S'LOW = B S'HIGH = D S'BASE'LEFT = A T'VALUE("E") = E T'POS(A) = 0 S'POS(B) = 1 T'VAL(4) = E S'SUCC(B) = C S'PRED(C) = B S'LEFTOF(B) = C S'RIGHTOF(C) = B

color_c := COLOR'left; -- Red color_c := COLOR'right; -- Violet color_c := COLOR'low; -- Red color_c := COLOR'high; -- Violet color_c := COLOR'leftof(Green); -- Yellow color_c := COLOR'rightof(Green); -- Blue color_c := COLOR'pred(Green); -- Yellow color_c := COLOR'succ(Green); -- Blue color_c := COLOR'val(1); -- Orange v8 := COLOR'pos(Green); -- 3 color_d := COLOR_REV'left; -- Violet color_d := COLOR_REV'right; -- Green color_d := COLOR_REV'low; -- Green color_d := COLOR_REV'high; -- Violet color_d := COLOR_REV'leftof(Blue); -- Indigo color_d := COLOR_REV'rightof(Blue); --Green color_d := COLOR_REV'pred(Blue); -- Green color_d := COLOR_REV'succ(Blue); -- Indigo color_d := COLOR_REV'val(3); -- Green -- (see COLOR) v8 := COLOR_REV'pos(Blue); -- 4 --(see COLOR) Data Properties Example (2) typeCOLOR is(Red, Orange, Yellow, Green, Blue, Indigo, Violet); -- Red-0 Orange-1 Yellow-2 Green-3 Blue-4 Indigo-5 -- Violet-6 subtypeCOLOR_REV isCOLOR range Violet downto Green; -- (Violet, Indigo, Blue, Green) -- Violet-6 Indigo-5 Blue-4 Green-3 ... ... variable color_c: COLOR := Blue; variable color_d: COLOR_REV := Blue; variable v8: integer;

Data Properties (Array) A'LEFT[(N)]Left bound of Nth index range A'RIGHT[(N)]Right bound of Nth index range 21 A'LOW[(N)]Lower bound of Nth index range A'HIGH[(N)]Upper bound of Nth index range A'RANGE[(N)]Range of Nth index from left to right A'REVERSE_RANGE[(N)] Range of Nth index from right to left A'LENGTH[(N)]The number of values in the Nth index range

v8 := v30'left; -- 7 v8 := v30'right; -- 0 v8 := v30'low; -- 0 v8 := v30'high; -- 7 v8 := v30'length; -- 8 v8 := v31'left; -- 10 v8 := v31'right; -- 17 v8 := v31'low; -- 10 v8 := v31'high; -- 17 v8 := v32'left; -- 7 v8 := v32'right; -- 0 v8 := v32'low; -- 0 v8 := v32'high; -- 7 v8 := Bit_8'length; -- 8 v8 := Byte_table2'length(1); -- 4 v8 := Byte_table2'length(2); -- 8 v8 := Bit_4_8'length(1); -- 4 v8 := Bit_4_8'length(2); -- 8 Data Properties (Array Example 1) type Bit_8 is array (7 downto 0) of bit; type Bit_4_8 is array (0 to 3, 7 downto 0) of bit; ... constant Byte_Table2 : Bit_4_8 := ( ('1', '0', '1', '1', '0', '0', '0', '1'), ('0', '0', '0', '1', '1', '0', '1', '1'), ('0', '1', '0', '0', '0', '1', '0', '0'), ('1', '0', '0', '0', '1', '1', '0', '1')); ... variable v30: std_logic_vector(7 downto 0) := "11011111"; variable v31: std_logic_vector(10 to 17) := "11001010"; variable v32: Bit_8; …

Data Properties (Array Example 2) signal A: STD_LOGIC_VECTOR(7 downto 0); A'LEFT = 7 A'RIGHT = 0 A'LOW = 0 A'HIGH = 7 A'RANGE = 7 downto 0 A'REVERSE_RANGE = 0 to 7 A'LENGTH = 8

Data Properties (Physical Type to integer) type Current is range 100 to 1000000000 –- start form 100 -- instead of 0 units nA; uA = 1000 nA; mA = 1000 uA; A = 1000 mA; end units; ... Variable Cur : Current := 1 mA; ... v8 := Current'pos(Cur); -- v8 = 1000,000

Agenda • Data Type • Data Properties • Data Object • Constant • Variable • Signal • Alias • Operation

Constant • Definition constantNameList : Type [:=Value]; • Value Assignment Name :=Value;

Constant Example constante: real:= 2.71828; constantdelay: Time:=5 ns; constantmax_size : natural; ... ... max_size:=100;

Variable • Definition VariableNameList : Type [:=DefaultValue]; • Value Assignment [Label:]Name:= Expression;

Variable Example variablecount : natural := 0; variabletrace : bit; ... ... trace := '1'; trace := '0';

Variable Example (1) signal S, A : std_logic; ... ... process variableV, W: Std_logic; begin wait until Clock = '1'; V:=A nand W; S <= V; end process;

Signal • Definition signalNameList : Type [ Kind] [:= Expression]; • Value assignment Target<=Expression[after TimeExpression], Expression [after TimeExpression], ... ;

Signal Example (1) signalA, B, C: std_logic; signalH: std_logic_vector(1 downto 0); ... A <= B; A <= B nand C; -- Required resolution function A <= B nand Cafter0.2 ns; H <= "00", "01"after10 ns, "10"after20 ns; H(1) H(0) 10 ns 20 ns

VHDL Simulation & Synthesis Data Types