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Summary of results for Laser annealing survivability test. Testing still in progress.

Summary of results for Laser annealing survivability test. Testing still in progress. ‘ Handled ’ involves taking the chips through LA process with no equipment turned on. ‘ Heated ’ involves everything except the laser. ‘ LA ’ is the full laser anneal process.

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Summary of results for Laser annealing survivability test. Testing still in progress.

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  1. Summary of results for Laser annealing survivability test. Testing still in progress. ‘Handled’ involves taking the chips through LA process with no equipment turned on. ‘Heated’ involves everything except the laser. ‘LA’ is the full laser anneal process. Set 0 is the first LA test, done on implanted device. The annealed device recovered from implant damage. Set 1 was an attempt to recreate the results of Set 0. The devices did not survive, suspected a static issue. Set 2 used different devices. We have more, and the devices themselves have higher yields than AFSiD devices. Set 3.0 and Set 3.1 are being processed in parallel. The Set 3.0 chip is one step ahead of Set 3.1, allowing us to find and correct problems without loss of all devices. * Devices were received already bonded † 80% yield when ignoring mechanical failure

  2. First laser anneal test (P2). Device was implanted with 14keV P+ ions, and IDS showed decreasing channel conductance. The device recovered partially between implant and re-testing prior to laser anneal test, and further after annealing. Sample IV curve for subsequent failed test. Device is WPOMP1D2 from W14D5. Red curve shows expected MOSFET action before the test, which is lost (blue) after laser annealing. Before (right) and after (left) IV curves for RTA test. (23/07/2010, ANU) Failure mode suggests migration of dopants from leads into channel. Chips had wire bonds removed, then remaining Al etched with acid bath before rebonding.

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