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Effects of VLSI fault models and distributed systems failure models: A hardware designer’s view Gottfried Fuchs fuchs@e

Effects of VLSI fault models and distributed systems failure models: A hardware designer’s view Gottfried Fuchs fuchs@ecs.tuwien.ac.at. Faults considered in VLSI. stuck-at (0/1) stuck open delay …. 1. 1. 1. ?. 0. 1. ?. 0. 1. 1. -> 0. SA0. 0. +/- D.

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Effects of VLSI fault models and distributed systems failure models: A hardware designer’s view Gottfried Fuchs fuchs@e

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  1. Effects of VLSI fault models and distributed systems failure models: A hardware designer’s viewGottfried Fuchsfuchs@ecs.tuwien.ac.at Gottfried Fuchs

  2. Faults considered in VLSI • stuck-at (0/1) • stuck open • delay • … 1 1 1 ? 0 1 ? 0 1 1 ->0 SA0 0 +/-D Gottfried Fuchs

  3. Failures considered in distributed systems • crash • omission • byzantine Node 1 Node 2 arbitrary behavior! msg msg msg Node 3 Gottfried Fuchs

  4. Mapping of VLSI Faults to failures in distributed systems 1 1 1 1 1 1 SA0 +/-D Gottfried Fuchs

  5. Byzantine tolerant tick-sync in VLSI: The DARTS example on booting do: send tick(0) to all [once]; clock:= 0; continuously do: If received tick(m) from at least f+1 remote nodes with m > clock: send tick(m) to all [once]; clock:= m; If received tick(m) from at least 2f+1 remote nodes with m >= clock: send tick(m+1) to all [once]; clock:= m+1; Gottfried Fuchs

  6. Properties of DARTS • n>=3f+2 fully connected nodes O(n2) links • 4 threshold modules per node (“f+1”, “2f+1”) for falling/rising ticks • threshold modules f+1 resp. 2f+1 -out-of-3f+1 scale very unfavorable in standard cell CMOS • area effort scales with: 3f+1 choose f+1 cf. implementations for f=2 vs. f=3:3-out-of-7 vs. 4-out-of-10 leads to area increase by factor of 11 Gottfried Fuchs

  7. (What) can we do better? Gottfried Fuchs

  8. Simpler algorithms 1/2 ;Omission tolerant algorithm on booting do: send tick(0) to all [once]; clock:= 0; continuously do: If received tick(m) from at least 1 remote node with m >= clock: send tick(clock),…, tick(m) to all [once]; clock:= m; If received tick(m) from at least f+1 remote nodes: send tick(clock+1) to all [once]; clock:= clock+1; • n>=2f+2 nodes required • two rules (“f+1”, “1”) one trivial (OR-gate) Gottfried Fuchs

  9. Simpler algorithms 2/2 • only n>=f+2 nodes required • only one trivial rule (OR-gate as threshold module) ;Crash tolerant algorithm on booting do: send tick(0) to all [once]; clock:= 0; continuously do: If received tick(m) from at least 1 remote node with m >= clock: send tick(clock),…, tick(m) to all [once]; clock:= m; Gottfried Fuchs

  10. Algorithm cost comparison oftick-synchronization designs • Substantial savings for weaker failure models • less nodes • less links • dramatically reduced area Gottfried Fuchs

  11. Algorithm cost comparison oftick-synchronization designs Threshold modules are main contributor to area factor of 14,5 factor of 50 factor of 108 factor of 20 Dagstuhl seminar DA and VLSI, September 2008 Gottfried Fuchs 11

  12. Mapping of VLSI Faults to failures in distributed systems But remember! 1 1 1 1 1 1 SA0 +/-D Gottfried Fuchs

  13. Questions and issues • Can we derive failure models and algorithms which are more suitable for VLSI? • Threshold modules are essential for FT circuits: efficient library cells/macros are needed! • Analysis of hardware fault types and probabilities are needed: How many faults are Byzantine? • Metastability issues prohibit 100% fault coverage even for designs of Byzantine tolerant algorithms: • How much coverage can we achieve? • How much coverage can we achieve with HW designs of weaker failure models? Gottfried Fuchs

  14. Thank you for your attention! comments, questions, solutions? Gottfried Fuchs

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