Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004

1. Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Memory System for Micro Satellite Final A Presentation

2. Problems In Space • Short time “Bit Flips” • Permanent malfunction –“Latch Ups” Memory is especially vulnerable to these kind of failures ! Goal : Building a reliable Memory System ! Memory System for Micro Satellite

3. Block Diagram of Conventional Memory System Generator Bus Memory Controller Memory Memory System for Micro Satellite

4. Block Diagram of a Memory System Using 3 Memory Controllers Upon a Bus Memory Controller 2 Memory Generator Bus Memory Controller 3 Memory Memory Controller 1 Memory Memory System for Micro Satellite

5. Single EDAC Based Memory System (using TMR) Memory Controller 2 Memory Generator EDAC Bus TMR Memory Controller 3 Memory Memory Controller 1 Memory Memory System for Micro Satellite

6. Optimal Memory System Opt Memory Module 2 Memory Generator Bus TMR Opt Memory Module3 Memory Opt Memory Module 1 Memory Memory System for Micro Satellite

7. Demands From Memory Module • Transparency to user • Modularity • Provide Reliability (use of EDAC) • As fast as possible • Minimizing implementation failures – using “black boxes” Memory System for Micro Satellite

8. EDAC Connection Between SDRAM Controller and Memory Memory Code EDAC Parity Memory Module PLB IPIF SDRAM Controller Bus IPIC Memory Memory System for Micro Satellite

9. EDAC Connection Between SDRAM Controller and PLB IPIF Memory Module PLB IPIF SDRAM Controller Bus IPIC EDAC Memory Memory System for Micro Satellite

10. Optimal Memory Module Optimal Memory Module SDRAM Controller 1 Memory Code EDAC Parity PLB IPIF Bus IPIC SDRAM Controller 2 Memory Memory System for Micro Satellite

11. Theoretical & Actual Performance Theoretical max BW of SDRAM is 400 MB/Sec: • SDRAM operating frequency : 100 MHz • 32 bits of data = 4B • Refresh Period = 4096 cycles Actual SDRAM performance: • SDRAM transaction time = 4 + 1*BL [cycles] • BL := Burst Length in SDRAM Transaction • Efficiency factor (EF) = BL/(4+BL) • Actual frequency = EF*100Mhz Memory System for Micro Satellite

12. BW for up to 32bit transactions with single read/write is 80 MB/Sec: • 32 bits of data = 4B = 1[BL] => EF = 0.2 => Actual Frequency = 20Mhz BW for single PLB transaction (64 bit) is 132 MB/Sec: • 64 bits of data = 8B = 2[BL] => EF = 0.33 => Actual Frequency = 33Mhz • SDRAM handles 32bit (4B) in each cycle Memory System for Micro Satellite

13. Reliability vs. Delay • EDAC unit adds E delay cycles • TMR unit adds R delay cycles • Rewriting data = Memory Module Time (MMT) = EDAC + SDRAM = E + 4 + BL Memory System for Micro Satellite

14. Hardware Constraints • SDRAM memory chip • Data width : 16 bit = 2B • TMR simulation will multiply each SDRAM transaction and each EDAC rewrite 3 times (for each memory module) Memory System for Micro Satellite

15. Reliable Memory System Performance (without hardware constraints) T = TMR + SDRAM transaction + rewrite + rewrite = R + (3)(MMT) = R + (3)( E + 4 + BL) [cycles] EF = BL/[R + (3)(E+4+BL)] TMR EDAC Memory System for Micro Satellite

16. Reliable Memory System Performance (with hardware constraints) T = TMR + (3)SDRAM transactions + (3)rewrites + (3)rewrites = R + (9)(MMT) = R + (9)( E + 4 + BL) [cycles] EF = BL/[R + (9)(E+4+BL)] EDAC TMR Memory System for Micro Satellite

17. Reliable Memory System Performance – No Error Occurs T = TMR + SDRAM transaction = R + MMT = R + E + 4 + BL [cycles] EF = BL/[R + (E+4+BL)] Memory System for Micro Satellite

18. Example Let’s review a system with smallest delays: • E = 1 cycle • R = 1 cycle BW for single PLB transaction (64 bit) • 64 bits of data = 8B = 4[BL] • Reliable system with hardware constraints: EF = 0.049 => Actual Frequency = 4.9Mhz => BW = 9.8MB/s • Reliable system without hardware constraints: EF = 0.143 => Actual Frequency = 14.3Mhz => BW = 28.6MB/s • SDRAM handles 16bit (2B) in each cycle Memory System for Micro Satellite

19. Example - continue • Reliable system (no error occurs): EF = 0.4 => Actual Frequency = 40Mhz => BW = 80MB/s • Conventional system: • comparing with 32bit data width SDRAM (no parity) EF = 0.333 => Actual Frequency = 33.33Mhz => BW = 132MB/s Memory System for Micro Satellite

20. Optimal Memory System (under test) Opt Memory Module 2 Memory Generator Bus TMR Opt Memory Module3 Memory Corruption Unit Opt Memory Module 1 Memory Memory System for Micro Satellite

21. Completed Tasks • Study the Virtex-II Pro component design. • Study the PPC405 Processor core • Study the VHDL development environment and VHDL. • Writing a tester hardware of the LED’s – from VHDL design through synthesis, and place&route using Xillinx EDK. Done Done Done Done Midterm Memory System for Micro Satellite

22. Completed Tasks (continue) • Writing a tester software with use of UART capabilities (Telnet). • Building up a standard computer system and writing an application to test its memory. • Design architecture of reliable memory system and internal memory modules Done Done Done Final Memory System for Micro Satellite

23. Second Semester Goals • Study the probability model of error in a memory system in space. • Implementation of the designed memory system. • Connect module to IPIF • Implement the optimal memory module. • Implement the optimal memory system. • System testing • Debug. • Implement a memory corruption unit. • System integration of the memory system in a complete computer system. Done Done 3 weeks 3 weeks 2 weeks 2 weeks 3 weeks Memory System for Micro Satellite