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Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA

Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA. Taeweon Suh § , Hsien-Hsin S. Lee § , Sally A. Mckee † , and Martin Schulz ♀ § Georgia Institute of Technology , † Cornell University, and ♀ Lawrence Livermore National Laboratory.

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Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA

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  1. Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA Taeweon Suh§, Hsien-Hsin S. Lee §, Sally A. Mckee †, and Martin Schulz ♀ § Georgia Institute of Technology, †Cornell University, and ♀Lawrence Livermore National Laboratory

  2. Owl: System-wide Monitoring • Overcome traditional sampling,counter-based performance monitoring • Proposed general framework for system-wide monitoring called Owl • Monitoring capsule can be deployed anywhere in a system • Each monitoring capsule consists of FPGA cells to hold monitoring modules as well as standardized hardware interfaces • Pre-built monitoring modules are dynamically deployed in monitoring capsule’s FPGA fabric M CPU CPU M M M L1 Cache L1 Cache M M L2 Cache L2 Cache M M M M Memory M I/O Bridge M M Georgia Tech, Cornell, LLNL - WARFP 2005

  3. Monitor Monitor Monitor Cross CapsuleAnalysis Example: Multi-level Memory Monitoring CPU L1 Cache L2 Cache Main Memory Georgia Tech, Cornell, LLNL - WARFP 2005

  4. Feasibility Study • IPC perturbation according to different injection rates (IR) of all L1 traffic • Simplescalar-4.0 alpha with bus and SDRAM models • In this work, we conduct a feasibility study with a rapid prototyping environment using FPGA platform Georgia Tech, Cornell, LLNL - WARFP 2005

  5. Virtex-II Pro Microblaze Monitoring Capsule for D-Cache OPB DDR SDRAM controller Ethernet controller UART Microblaze-based Evaluation Platform • D-Cache behavior monitoring Xilinx ML310 board Serial JTAG Ethernet Georgia Tech, Cornell, LLNL - WARFP 2005

  6. Virtex-II Pro PowerPC 405 Monitoring Capsule for D-Cache Ethernet controller PLB OPB Bridge DDR SDRAM controller UART PowerPC-based Evaluation Platform • D-Cache behavior monitoring Xilinx ML310 board Serial JTAG Ethernet Georgia Tech, Cornell, LLNL - WARFP 2005

  7. Xilinx ISE 6.3 Add Monitoring Capsule Deploy a Monitoring Module Synthesize & Place & Route Debugging with Evaluation Hardware Design Flow Xilinx EDK 6.3 Base System Builder Add CPU, DDR controller Ethernet controller, UART, Interrupt Controller Georgia Tech, Cornell, LLNL - WARFP 2005

  8. Owl Evaluation Stack SPEC2000 uClinux running on Microblaze • Measure system perturbation adopting monitoring modules with different injection rates, by comparing execution times of SPEC2000 with/without monitoring Georgia Tech, Cornell, LLNL - WARFP 2005

  9. Owl Evaluation Challenges on FPGA platform • Memory on board is too fast, compared to processors in FPGAs • DDR SDRAM: 100MHz • Microblaze: 100MHz • => This can be solved by inserting wait cycles for memory transactions in monitoring capsule • Available processors (Microblaze, PowerPC405) in FPGAs are too simple to mimic the state-of-the-art superscalar processors • => However, Owl concept covers any complexity system, • which includes a rapid prototyped simple system like • Microblaze-based platform Georgia Tech, Cornell, LLNL - WARFP 2005

  10. Questions & Answers That’s All Folks ! Georgia Tech, Cornell, LLNL - WARFP 2005

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