Virtex-5 FPGA

IUCAA FOCAL PLANE ARRAY CONTROLLER (IFPAC)Inter-University Centre for Astronomy and Astrophysics, Pune, INDIA Clock card with a backplane during LAB tests USB 2.0 Virtex-5 FPGA Ethernet / RocketIO via SFP

Multi-FPGA, Multi-Interface, Scalable generic controller for wide variety of astronomical detectors • Basic Single FPGA, 2 card system can be used for TWO 4 output or ONE 8 output detector, with up to 1 M pixel/sec pixel rate per channel • Two Basic systems can be combined in Master-Slave fashion to double the functionality (i.e. 16 output detector controller) • More than two basic units can be run simultaneously and in sync for Mosaics. • Detector and observation specific ROI readout clock generation for up to 16 output detector. • 4 Ch. Single board version with DCDS is being developed to use for ZTF and WasP instruments at Palomar IUCAA FOCAL PLANE ARRAY CONTROLLER (IFPAC)

IUCAA FOCAL PLANE ARRAY CONTROLLER (IFPAC) THANK YOU For more information please come and have a look at my poster which is located at L14.

Virtex-5 FPGA

Virtex-5 FPGA

Presentation Transcript

SOC FPGA Design Lab Discussion 5

Xilinx Virtex-5 FPGA Clocking

Experience powering Virtex-7 FPGAs

FPGA

General Purpose FIFO on Virtex-6 FPGA ML605 board

DDRIII BASED General Purpose FIFO on Virtex-6 FPGA ML605 board PART B presentation

FPGA

DDRIII BASED General Purpose FIFO on Virtex-6 FPGA ML605 board PART A presentation

SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA

Lecture 5 Key Locker using FPGA

CHAPTER 6 Virtex Memory

FPGA

FPGA

Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA

Irradiation Test of the Virtex-5 Muon Port Card Mezzanine

FPGA

FPGA

Introduction To VIRTEX II Architecture

Virtex-6 Investigations

First Results from Radiation Tolerance Tests on Xilinx Virtex 5

Reconfigurable FPGAs (The Xilinx Virtex II Pro / ProX FPGA family)