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Lecture 08: Logic Families to Implement Gates

Lecture 08: Logic Families to Implement Gates. PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING. How to Construct Logic Gates?. Various logic families exist: Diode transistor logic (DTL) Transistor transistor logic (TTL) Emitter Coupled Logic (ECL)

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Lecture 08: Logic Families to Implement Gates

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  1. Lecture 08: Logic Families to Implement Gates PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

  2. How to Construct Logic Gates? • Various logic families exist: • Diode transistor logic (DTL) • Transistor transistor logic (TTL) • Emitter Coupled Logic (ECL) • Complementary Metal Oxide Semiconductor (CMOS) Logic • CMOS is almost universally used today.

  3. Diode Transistor Logic • Uses semiconductor diodes and bipolar transistors, along with resistances. 2-input AND gate 2-input NAND gate

  4. Transistor Transistor Logic 2-input NOR gate 2-input NAND gate

  5. Basic Concepts of Switch Based Circuits • They rely on the operation of tiny switches, which can be in one of two states. • open or closed, ON or OFF, voltage or no voltage, etc. • Switch open: • No current flows. • Light is OFF. • Switch closed: • Current flows. • Light is ON. V

  6. Digital Voltage Ranges and Noise Margin • A range of voltages is treated as logic 0, while another range of voltages is treated as logic 0. • The exact range of voltages depends on the implementation technology. • For reliable operation of circuits, there must be considerable gap between the two ranges, called noise margin. • Example for Transistor Transistor Logic (TTL) family: 0 1 Digital Value Noise Margin Analog Value 0 V 0.8 V 2.0 V 5 V

  7. n-type MOS Transistor • When Gate has positive voltage, there is low resistance between source and drain (points #1 and #2) – switch closed. • When Gate has zero voltage, there is high resistance between source and drain (points #1 and #2) – switch open. Gate = 1 Gate = 0

  8. p-type MOS Transistor • When Gate has positive voltage, there is high resistance between source and drain (points #1 and #2) – switch open. • When Gate has zero voltage, there is low resistance between source and drain (points #1 and #2) – switch closed. Gate = 0 Gate = 1

  9. Complementary MOS (CMOS) NOT Gate

  10. CMOS NAND Gate

  11. CMOS NOR Gate

  12. CMOS AND Gate • Requires composition: a NAND gate followed by a NOT gate.

  13. CMOS OR Gate • Requires composition: a NOR gate followed by a NOT gate.

  14. END OF LECTURE 08

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