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POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS

POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS. I. Bucur , N. Cupcea , C. Stefanescu , A. Surpateanu Computer Science and Engineering Department, University Politehnica of Bucharest, Romania Semiconductor Conference, 2009. CAS 2009. International. Outline. Introduction Background

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POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS

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  1. POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS I. Bucur, N. Cupcea, C. Stefanescu, A. Surpateanu Computer Science and Engineering Department, University Politehnica of Bucharest, Romania Semiconductor Conference, 2009. CAS 2009. International

  2. Outline • Introduction • Background • Algorithm • Experimental result • Conclusion

  3. Introduction • Power consumption is becoming one of the most important considerations in VLSI design. • Especially in FPGA design. • In this paper is presented a new mapping approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits.

  4. Background FPGA POWER • Static power :current leakage in transistors • Dynamic power :signal transitions between logic-0 and logic-1•Functional transitions - necessary for the correct operation of the circuit•Glitch - unbalanced delays to the inputs of a logic gate (effect on power consumption)

  5. Dynamic powern : the number of nets in the circuitSi : the switching activity of net ICi : the capacitance of net If : the frequency of the circuitVdd: the supply voltage

  6. Net switching activity estimation - probability approaches • simulation-based approaches This paper uses simulation-based simulator of SIS-1.2 • This gate-level simulations provide both the functional and total activity. • Spurious transition activity is computed as the difference between them.

  7. Technology mappingtransforms the gate-level network into a network of cells in the target technology library.

  8. Algorithm • K-feasible-cones enumeration from PIs to POs • Make the selection among the K-feasible cones of each node guided using critical path in circuits and several appropriate cost functions from POs to PIs

  9. Depth Metric for node u is computed over one of the best depth K-feasible cone of u to quantify the depth criterion: • In order to quantify the best suitable cone rooted in u is introduced the cost function bestCone. It is locally applied for the entire set of K-feasible cones of the node u:

  10. Multi-criteria function multiCritis implemented as follows

  11. |LUT(v)|: the number of internal nodes of cone v previously (already) chosen as LUTs, • |cone(v)|: the number of internal nodes of cone v. • activity(w): the spurious logic activity estimation of the node w • |fanout(w)|: the number of nodes connected to the output of node w • q1 (w) = 1 iff |fanout(w)| < 3 • q1 (w) = 0 iff |fanout(w)| >= 3 • q2 is the parameter controlling the influence of the spurious activity estimation in multi-criteria cost

  12. First part of multiCrit • The numerator of the quotient penalizes node duplications by increasing the cost of cuts that encapsulate nodes that have already been labeled as root nodes. • The denominator rewards cuts that encapsulate many nodes that have not been labeled as root nodes. Second part of multiCrit • The q1 factor minimizes node duplication by favoring cuts that reuse nodes. The activity factor minimizes the switching activity of the connections. • The fanout size factor rewards cuts that have high-fanout input nodes.

  13. High-fanout nodes are difficult to encapsulate entirely-attempting to encapsulate them results in unnecessary node duplication. • This is avoided by choosing high-fanout nets as root nodes. • Using this cost function, nodes with large fanouts are likely to be chosen as root nodes. • Both parameters, q1 and q2, were experimentally determined. Best results were obtained when q2 >> q1 reflecting the preference for optimizing power over depth.

  14. Experimental result • To estimate power consumption using, it is required the capacitance of each net. The fanout of each mapped node was considered as an estimate of the capacitance of it • Optimum depth: keep optimum depth and search among power-aware equivalent solutions • Optimal depth: optimal depth but performing with improved spurious power consumption. • Optimal depth & area: optimum depth, with minimal area (number of used LUTs)

  15. Conclusion • Trade-off between dynamic power and area. • Power-driven mapping both for depth and area optimal, it appears to be more complex than mapping only for optimal depth. • Actual working heuristics have to be upgraded because it was searched only a limited part of mapping solutions’ space. • It is intended in the future approach to use dynamic programming together with refined heuristics to further develop PwDrvMapalgorithm.

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