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TECHNION-ISRAEL INSTITUTE OF TECHNO

TECHNION-ISRAEL INSTITUTE OF TECHNO DEPARTMENT OF ELECTRICAL ENGINEERING HIGH SPEED DIGITAL SYSTEM LABORATORY. FINAL REPORT PROJECT A SUBJECT: CONNECTING VIDEO CAMERA TO PC VIA DSP PERFORMED BY:

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TECHNION-ISRAEL INSTITUTE OF TECHNO

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  1. TECHNION-ISRAEL INSTITUTE OF TECHNO DEPARTMENT OF ELECTRICAL ENGINEERING HIGH SPEED DIGITAL SYSTEM LABORATORY FINAL REPORT PROJECT A SUBJECT: CONNECTING VIDEO CAMERA TO PC VIA DSP PERFORMED BY: MAXIM DUBOSSARSKY 313989386 BORIS YAROVOY 319445722 SUPERVISOR: MICHAEL ITZKOVITZ

  2. GENERAL DESCRIPTION • Connecting video camera to PC with help of two DSP • boards in order to enable processing, viewing and • storing video data by local users via network in real time • first board intended for receiving and processing • of video frames from video camera • second board intended for additional processing(optional) • and transferring video data from first board to PC

  3. system components • TMS320C6711 Imaging Developer’s Kit for • receiving and processing : • 16 MB of 100MHz SDRAM • DSP 6711withtwo Multichannel buffered Serial Port • VideoCard with decoder • TMS320C6701 Evaluation Module for PCI connection : • 8MB of 100MHz SDRAM • DSP 6701with two Multichannel buffered Serial Port • Connection to PCI bus (PCI controller)

  4. project target PROJECT TARGET IS TO TRANSFER VIDEO STREAM FROM VIDEO CAMERA TO COMPUTER IN ORDER TO SHOW IT ON A SCREEN

  5. SYSTEM DESCRIPTION EVM 6701 IDK 6711 McBSP PCIBUS PC McBSP IN OUR PROJECT WE TAKE CARE OF RECEIVING DATA FROM McBSP, TRANSFERRING IT TROUGH EVM PCI BUS CONNECTION AND STORING IT IN PC

  6. detailing of project task • Working process could be divided into 3 parts: • Receiving and storing data in memory of EVM • Transmitting data to PCI bus from the memory • Receiving and storing data in PC • Such division appropriates to our realization in program • There is also stage of integration between EVM program • and IDK one and transmitting and receiving on PCI bus In advance each part will be described in details

  7. Transfer: McBSP to McBSP IDK EVM McBSP-Slave McBSP-Master 32 bits of DATA Receiver CLKR CLKX Transmitter FSR FSX DR DX CLKG FSG Sample rate Generator Sample rate Generator CLKS = CPUclk/2 Events/ Interrupts Events/ Interrupts REVT XEVT To DMA To EDMA FS(R/X) – (receive/transmit) Frame synchronizationCLK(R/X) – (receive/transmit) Clock synchronizationREVT -read sync event for DMAXEVT - write sync event for EDMA The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX) and the other device the McBSP communicates to is a slave. The maximum bit rate for McBSP-to-McBSP communications is 35.71 Mbps and achieved when the master clock is CPUclk/2.

  8. receiving and storing data on EVM • EVM receives continuous data from 2 McBSB channels • simultaneously: 32K each one alternately • receiving performed by DMA mechanism: one DMA • channel allocated for each McBSP one and they stores • data in SDRAM memory • SDRAM organized as 3 buffers, each of 64K size and • they are filled in circular mode • To ensure memory allocation in SDRAM memory PRAGMA • macro was used Remark: all elements of 32 bit size and all sizes referred to such elements

  9. receiving and storing data on EVM IDK EVM SDRAM 32K DMA Buff0 Buff1 Buff2 32K Mcbsp0 Channel0 32K 32K 32K 32K PCI McBSP1 32K Channel1 32K 32K 32K Graphical representation • To synchronize DMA write transfers McBSP events are used • PCI and writing process to memory work in different rates • so triple buffering scheme is used

  10. sincronization of writing and reading to SDRAM There is array of flags in the program (one to each buffer) which are set on only when corresponding buffer is full Each buffer is filled up after two 32K transfers of two DMA channels are finished. After each transfer DMA and McBSP channels are reinitialized for the next one. All these actions and also implementation of buffer circular mechanism are done in ISR of DMA channel.

  11. Transmitting data to PCI PCI Controller SDRAM DMA buffer0 PCI bus channel2 FIFO 8*32bit buffer1 interrupt buffer2 Data is taken from SDRAM by DMA channel by 64K transfers Transfers are triggered by FIFO interrupt(connected to external pin 6 of EVM DSP)

  12. Recieving data on PC P C I EVM support function Buffer In SDRAM 64K Buffer 8 elements depth Position variable Data received by TI’s EVM support driver function Each transfer is of 64K elements. After buffer in SDRAM is filled up new data overwrites old

  13. Syncronization between DSP and PC PCI Controller P C I EVM support function PC MailBox DSP sends message to the host every time when 64K buffer is ready

  14. system performance Maximum transfer rate McBSP 6711 35.7Mbps 6701 55.56MbpsEDMA 1.2GbpsDMA 2.4Gbps EMIF to PCI 96MbpsPCI 1.03Gbps These rates are not achieved in the project. Reasons for this are described below.

  15. Critical Points • After every 32K DMA transfer (one half of buffer)the McBSP and DMA channels are closed and reopened and reinitialized, so bandwidth is narrowed. • Reading from PCI bus is performed in burst mode but McBSP frequency is lowered by 2 • PCI bus doesn’t achieve its theoretical bandwidth so reading from SDRAM is slower then writing to it from McBSP.

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