Ratioed Circuits

1. Ratioed Circuits • Ratioed circuits use weak pull-up and stronger pull-down networks. • The input capacitance is reduced and hence logical effort. • Correct operation depends on correct pull-up and pull-down ratio. • Ratioed circuits dissipate static power and must be used sparingly. • The pull-up network for ratioed CMOS (pseudo-nMOS) uses a single pMOS whose gate terminal is grounded (device is always on). • To compute the logical effort of the pseudo-nMOS gates we use the full complementary CMOS inverter as reference. • Assume that the full complementary CMOS inverter delivers current I in both rising and falling transition and that a properly sized pMOS device in a pseudo-NMOS circuit has its width ½ that of the nMOS pull-down network. • The logical effort is given by the ratio of the pseudo-nMOS inverter input capacitance to that of the unit CMOS inverter input capacitance.

2. Ratioed Circuits • The objective is to have the nMOS pull-down network sized appropriately to effectively fight the pMOS device for correct output. • The output current is therefore the difference between the pull-down current and the pull-up current. • The parasitic delay p is determined by comparing the parasitic output capacitance of the pseudo-nMOS inverter to that of the unit sized inverter. • A Pseudo-nMOS NAND can be shown to be generally slower than static CMOS, but pseudo-nMOS style shows improved delay for gates such as the NOR gate. Why? • Ganged CMOS is widely known as Majority gate. • A single configuration can perform different logic functions depending on input values.

3. Cascode Voltage Switch • Cascode voltage switch logic (CVSL) eliminates the static power consumption of the pseudo-nMOS design style. • It has a pair of nMOS pull-down networks to compute an output and its complementary value from associated input signals and their complementary values. • The pull-down networks are complementary with one side having series transistors while the other has a parallel combination. • CVSL has the potential to improve switching speed since the gate input capacitance is reduced.

4. Dynamic Circuits • The drawbacks of ratioed logic include: • Slow rising transitions • Contention on the falling transitions • Static power dissipation and • Non-zero output low voltage • Dynamic circuits require a precharge and evaluate phase and use a clock to circumvent the problems of the pseudo-nMOS approach. • Dynamic circuits are fast because of lower input capacitance and no contention during switching. • Dynamic circuits have zero static power dissipation?????? • The clock and the associated logic consume considerable dynamic power. • Dynamic circuits are sensitive to noise during evaluation.

5. Domino Logic • Floating nodes could result when the input transitions from a HIGH to a LOW before the precharge signal is asserted. When this condition occurs both the nMOS pull-down network and the pMOS (precharge devices are OFF. • Domino logic allows for the placement of static and dynamic circuits to eliminate floating nodes?????? • Domino gates are non-inverting. • Dual-rail domino logic gates encode each signal with a pair of wires. • The output and input signal pairs are denoted with _h and _l to indicate their status (high or low). • Inputs and their complementary values are accepted by dual rail domino. • These gates have both a precharge and an evaluate clock.