Lecture 5 Storage System

1. Lecture 5Storage System Memory System

2. Lecture 5: Memory System In this lecture, we will study • Storage Hierarchy • Main Memory • Main memory cell • Static Cell and Dynamic Cell • RAM • Organization of RAM chip • Construction Main Memory using RAM chips • Dynamic RAM and Refreshing • Main Memory Timing Parameters • Memory Bus Architectures • System Bus(single bus) architecture • 2-Bus architecture • Memory Bus and Multiple I/O Bus architecture Memory System

3. Lecture 5:Memory System • In this lecture, we will study(Continue) • Auxiliary Storage • Magnetic Tape • Disk • Moving Head Disk • Fixed Head Disk • Characteristics of Storage • Main Memory Addressing • Address Space and Storage Space • Method of accessing method using address • Method of representing address • Method of mapping address to the storage space • Precision of address • Addressing patterns of programs Memory System

4. Memory System • Storage Access Time and Storage Capacity have been the major limitations of the hardware resource to the programmers • Thus when you design a storage system, Time and Space must be traded off • If you need a very fast storage access time, you should have a large capacity main memory by sacrificing the storage capacity • If you need a very large storage capacity, you should have the secondary storage by sacrificing the storage access time Memory System

5. 2 Types of Storage Systems • System with a Single Storage System • Main Memory only • Embedded computers for simple applications • System with Hierarchical Storage System • Conventional system with Primary Memory and Secondary Storage • Primary Memory • Random Accessible(addressable) • Relatively small capacity • Secondary Storage(Auxiliary Storage) • Access through I/O class instructions via I/O bus or channel • Slower and cheaper than main memory Memory System

6. Storage Capacity Access Time Cost M1 S1 t1 C1 M2 S2 t2 C2 … … … … MS SS tS CS Storage Hierarchy Storage Hierarchy • Different storage M1, M2, … , MS, with different characteristics S1<S2<…<ss t1<t2<…<ts C1>C2>…>Cs • Storage Hierarchy provides; • Capacity: MS (Capacity = Capacity of the lowest level storage) • Access Time: t1 (AT= AT of the highest level storage) • Cost: CS (Cost= Cost of the lowest level storage) • e.g. M1- M2- M3 = Cache - Main Memory – Disk hierarchy • Capacity = Capacity of the Disk • Access Time = Access time of the Cache • Cost = Cost of the Disk Memory System

7. Memory Access • Two Registers are needed in CPU for memory access • MAR(Memory Address Register) • A register that needs to be stored with address by CPU for memory access • MBR(Memory Buffer Register or Memory Data Register) • A register that stores data for memory access • For Read access, memory puts the data read from memory • For Write access, CPU puts the data to be stored in memory • Read Access • CPU stores address into MAR and the CU sends Read control signal to Memory • Memory puts the data read from memory into MBR • Read data appears in MBR after the memory access time • Write Access • CPU stores address in MAR and data in MBR and CU sends Write control signal to Memory • Storing data completes after the memory cycle time Memory System

8. t R Read data available MBR Send address(MAR) Send address for the next access Access Time Cycle Time Memory Access Time/Cycle Time • Cycle Time • Time from a memory access to the next memory access • Access Time • Time from sending an address and Read control signal to the memory to the time when the read data is available Memory System

9. MAR address MBR data • MAR address • MBR data Main Memory Timing Parameters 2 different accesses; • Read Access • Write Access 2 different timing parameters; • Access Time From the time when address and control signal R is applied to the time when the data is in MBR. Represents the time when the read data is available. • Cycle Time From the time when address and control signal R is applied to the time when the next address and control signal R can be applied. Represents how often memory can be accessed. • Apply R(read) control signal to M Apply W(write) control signal to M In general Access Time < Cycle Time Memory System

10. Main Memory Main Memory • Only Storage that CPU can directly access • Random Access Memory • Random Access Memory is accessed by using Address • Each location in which a unit of information can be stored is assigned a unique address • Address is used to access a unit of information at the desired location • Access time is constant, i.e., independent of memory location or address • Memory Access • Read Access • Write Access Memory System

11. Memory System Memory Bank Memory Module Memory Module ... Memory Bank RAM RAM … … RAM RAM RAM RAM … … RAM RAM Memory Module Memory Module ... Main Memory Organization • Memory Cell • Memory Word(or Byte) • Block(or Page or Segment) • RAM Chip • Memory Module • Memory Bank • Memory System ... Memory System

12. Time Out • 매일 매일 일 때문에 바쁘게 살아가는 부부가 있었다. • 큰 아들이 신병훈련을 마치고 퇴소식을 갖게 되었으므로 부부는 그 식에 참석하러 가기로 했다. • 그들은 이 번 여행을 그들 둘만의 특별한 여행으로 만들고 싶었다. • 그들은 아들과 헤어진 후 five star 호텔에 투숙해서 호화판 저녁식사를 하며 즐겁게 보낸 다음 호텔 방으로 올라갔다. • 약 15분쯤 지나서 누가 방문을 두드렸다. 방문을 열어보니 아들이 환하게 웃으며 서 있었다. • “어머니 오늘 저녁을 어머니 아버지와 함께 지내려고 왔어요!” Memory System

13. SEL(address bit) SEL DI DO S Q SRF R Q’ DI DO cell R R(1: Read, 0: Write)(control signal) For an Access: SEL=1 Read: SEL . R Write: SEL . R’ Model of a Memory Cell Memory System

14. SRAM - Static Memory Chip Static RAM - SRAM • Preserve stored information as long as the power is on: Access Time and Cycle Time are approximately equal • Current demand is steady -> low cost power supply is OK • A cell is made of several transistors, thus chip density is lower than DRAM • Chip is organized in the form of (n x m)-bit(cell) • Allows to access m bits(usually m=8, a byte) in one access • Faster access time and more expensive than DRAM - For small quantity applications, SRAM pays off Memory System

15. DRAM - Dynamic Memory Chip Dynamic Cell - DRAM • Information is stored in the form of charge, thus, stored information is discharged as the time elapses even if power is on • Made of a single transistor, thus chip density is higher than SRAM • To preserve the stored information, needs periodic refresh, Refresh Cycle(2mSec) • Peak load for current • Usually refresh logic is provided on the chip • Access Time < Cycle Time • Chip is organized in the form of (n x 1)-bit • Allows to access 1 bit per access • Much slower access time than SRAM • For large capacity applications, DRAM pays off Memory System

16. Cell Array ... Refresh Buffer DRAM - Refresh Refresh Operation [1] All the cells in a selected row are read to the particular cells, one for each column in an extra row [2] From this extra row, cells in the selected row are recharged • Refresh by 1 row at a time, all the cells in a row together • 1 refresh operation requires the Row Address • m rows require m refresh operations • Refresh Counter • Provides a Row Address for a refresh operation • Counter advances for the next row address to refresh Memory System

17. Refresh Methods • Refresh Methods • Transparent • 1/2 of memory cycles to CPU and I/O and 1/2 for refresh • Cycle Steal • A Time-out signal generates a cycle steal request at the period of (Refresh Cycle Time / Number of row) to refresh a row • Burst • Refresh request is made in every refresh cycle to refresh all rows, one row by one in succession Memory System

18. Cell Layout in RAM Square layout of cells - Accommodate largest number of cells in the same chip area - e.g. 64 x 64 layout Memory System

19. DI0 DI1 DI2 . . . DI8 Write Amplifier . . . 0 1 2 7 SEL DI DO a0 a1 a2 R 0,0 0,1 0,2 0,7 Address Decoder Address 1,0 1,1 1,2 1,7 DI0 DI1 DI2 . . . DI7 a0 a1 a2 CS R/W 8 x 8 2,0 2,1 2,2 2,7 ... DO0 DO1 DO2 . . . DO3 7,0 7,1 7,2 7,7 CS Chip Select Read Buffer/Sense Amplifier . . . R/W DO0 DO1 DO2 DO7 (8 x 8) RAM Chip Organization Memory System

20. Number of chips to get m-bit word = m/q • Number of chips to get n words = n/p • Number of chips to get (n x m) memory = n/p × m/q Construction of Memory with RAM e.g. Construction of (1K × 32) Memory • (8 × 8) RAM Chips 1024/8 × x 32/8 = 128 × 4 = 512 • (64 × 1) RAM Chips • 1024/64 × 32/1 = 16 × 32 = 512 (n × m) Memory using (p × q) RAM Memory System

21. Data Bus (d8 ~ d15) Data Bus (d0 ~ d7) Address Bus (a0a1a2) Address Bus (a3) . . . . . . . . . . . . Memory Bus DI’s DI’s a0 a1 a2 DI’s DI’s DI’s DI’s DI’s a0 a1 a2 a0 a1 a2 a0 a1 a2 a0 a1 a2 CS R/W CS R/W CS R/W CS R/W U1 U2 U0 U3 DO’s DO’s DO’s DO’s . . . . . . . . . . . . Control Bus(R/W) (16 x 16) Memory Using (8 x 8) RAM Memory System

22. A0 A1 A2 A3 A4 Refresh A0 A1 A2 A3 A4 To memory a0 a1 a2 a3 a4 Refreshing DRAM: Refresh Counter 32 x 32 DRAM array Memory System

23. Main Memory System Bus . . . CPU I/O I/O Memory Bus Architecture System Bus - Simple single bus • Most often found in low cost PCs • Single bus prevents concurrent data transfers • CPU communicates with and controls I/O devices as it accesses memory • Both roles of memory and I/O buses, value on the address bus determines role of the bus Memory System

24. Memory Bus I/O Device CPU I/O Bus Main Memory ... I/O Controller (DMAC) I/O Device 2-Bus Architecture • CPU communicates with I/O over I/O Bus • CPU and DMA Controller access memory over Memory Bus • Permits high speed Memory Bus with short interconnection length • I/O data and I/O address bus width can be narrower than Memory Bus • Multi-port memory has internal scheme which handles and coordinates each port Memory System

25. Main Memory Memory Bus ... I/O Channel I/O Channel CPU To I/O Controllers and/or Adapters Memory Bus/Multiple I/O Bus Architecture • CPU, I/O Channels, and Memory communicate over Memory Bus • Several channels can be active at the same time • I/O channel multiplexes slower devices Memory System

26. Oak Valley resort in Fall Memory System

27. Auxiliary Storage Memory System

28. Auxiliary Storage • Sequential Access Storage Device(SASD) • Magnetic Tapes • Reel Tape • Cassette, cartridge • Direct Access Storage Device(DASD) • Magnetic Disks • Moving head disk - Diskette • Fixed head disk - Hard disk Memory System

29. File i block block block R1 R2 R3 R4 R5 IRG EOF Magnetic Tape • Storage Organization • Store Files, separated by EOF • Files consist of Blocks, separated by IRG(inter-record gap) • Blocks contain Records, a basic information unit • Tape Access - to read record R4 in Filei • Read in forward direction until EOF of Filei-1 • Continue read in forward direction Until the first IRG • Continue read • Sequential Access Memory System

30. Moving Head Disk Fixed Head Disk Sector m Sector 0 Track 0 Track 1 Track m Track Cylinder Surface Tracks Magnetic Disk Memory System

31. Magnetic Disk Address Drive No. / Surface No. / Track(Cylinder) No. / Sector No. Random Accessible Storage Access Time • Seek Time consists of • Time to position the read/write head to the desired track • Intra-Cylinder access does not need seek time • Fixed Head Disk does not have seek time unless current access requires to access from the different disk drive • Head Switching Time • Time to activate a head when the head used for the last access is different from the one that is going to be used for the current access • Both Moving and Fixed Head Disk require head switching time Memory System

32. RAM DASD SASD Access Time Seek Time Distance of Storage Locations Access Characteristics of Storage Systems Memory System

33. Memory Memory Bus DASD or SASD I/O Dev ... I/O Dev CPU CPU and I/O device(s) are competing to use memory bus, causing a Bottleneck at the Memory Bus Memory Bandwidth Use of Memory Bandwidth CPU - Read Instructions from memory Read Operands from memory Store Results to memory I/O - Initially read Program and Datafrom input device to memory before running - (Read Operands from input device to Memory for processing) - Write the Results of execution of the program to the output device Memory System

34. Address Space Memory Space Addresses visible to programmers Mapping Function Storage Locations Address • Address • Assigned to each stored object to retrieve the object later via its address • Eventually needed to be mapped onto a physical memory location • In most current systems,an Address and a Memory Locationare distinct concepts related by the Mapping Function • 1-1 mapping implies that the an address and the memory location are referred to synonymously • Address Space Memory System

35. Address Design Considerations • Efficient Specifications of addresses • Independence of Address Space • Services to users Memory System

36. Address Design Considerations:Address Specification Efficiency • Space considerations • Minimize the umber of bits to specify address in an instruction • Minimize the size of mapping tables, descriptors, etc • Time considerations • Minimize time to retrieve an operand, and update the address structure • Minimize the time for automatic generation of addresses by compiler Memory System

37. Address Design Considerations:Independence of Address Space • Relocatability • Speedy relocation of user jobs in Multiprogramming environment • Make the garbage collection fast • Portability • By uncoupling the address space from memory space program for one computer can be run in different computers Memory System

38. Memory System

39. Multiprogramming • CPU is the most expensive hardware resource • With respect to Memory, Secondary storage(such as disks), I/O • We would like to keep the CPU busy all the time • What makes CPU from busy all the time? • Mainly I/O operations including disk accesses • What can we do about it so that the expensive CPU time cannot be wasted? • Provide more jobs, i.e., have multiple of programs in the memory which are ready to be executed • When the execution of one job causes CPU idle, immediately initiate another job ready to be executed in the memory Memory System

40. Job 3 Multiprogramming Job 1 Job 2 Job 3 Job 3 Job4 Job4 Job 5 Waiting Job Waiting Job Waiting Job Memory System

41. Job 1 Job 2 Job 3 Job4 Job 5 Multiprogramming:Relocation Waiting Job Job4 Waiting Job Memory System

42. Job 1 Job 2 Job 3 Job4 Job 5 Multiprogramming:Relocation Job4 Waiting Job Waiting Job Job4 Memory System

43. Job 1 Job 2 Job 3 Job4 Job 5 Multiprogramming:Garbage Collection Job 2 Job 3 Job4 Job 5 Job 8 Job 6 Job7 Job 8 Memory System

44. Shared Routine job1 job1 Sub A • Reference • that needs • protection; • Security • Privacy job2 job2 Job3 (currently running) Job3 (currently running) Sub A job4 job4 Sub A Address Design Considerations:Services to Users • Provide illusion of much larger memory than the actual • virtual storage • Provide Protection and Sharing for Multiprogramming Sub A Memory System

45. Time Out • 오래 전부터 사업상 알고 지내는 두 남자가 함께 거리를 걸어가던 중 한 남자가 당황해 하며 말했다. • “야단났네, 내 마누라가 내 정부와 함께 이리로 오고 있어.” • “어이쿠!” 다른 남자가 말했다. “내 마누라와 정부도 함께 이리로 오고 있는데.” Memory System

46. Modes Operand Auto-increment [Rx] [Rx]+1 Auto-decrement [Rx] [Rx]-1 Basic Addressing Modes OP-code Ri Rx X Ri: Arbitrary address register Rx: Index Register Rb: Base Address Register Register Direct [Ri] Immediate X Direct M[X] Register Indirect M[[Ri]] Base + Displacement M[[Rb] + X] Indexed; M[X + [Rx]]; Base + Index M[[Rb] + [Rx] + X] Register-Memory Indirect M[M[[Ri]]] Memory Indirect M[M[X]] Memory System

47. Properties of address:Operand Access Method from the Specified Address • Direct Address: ADD X(EFA=X; AC <= AC+M[X] ) • 1 memory access per operand • Consumes a lot of instruction bits for a direct address • Indirect Address ADD @X(EFA=M[X]; AC <= AC+M[M[X]]) • At least 2 memory accesses per operand • Indirect by a bit flag(if MSB of the accessed address is 1 then further indirect) • Register indirection : 1 memory + 1 reg accesses per operand access • Calculated Address ADD $X(EFA=M[X+[R]]; AC <= AC+M[X+[R]]) • 1 memory access + 1 register access plus calculation per operand • Little shorter than direct address --> saves instruction bits • Immediate Address ADD #X(EFA=na; AC <= AC+X) • No memory access for operand • Consumes a lot of instruction bits Memory System

48. 100 200 250 125 200 213 Example ADD 100 Make an addition of the number 50 stored in AC(data register in CPU) and the operand obtained using 100. Assume that an address register Rb(Base Address Register) contains 150. What would be the results of additions? 100 is a direct address : 50 + 200 = 250 100 is an indirect address: 50 + M[M[100]] = 50 + M[200] = 50 + 125 = 175 100 is a calculated address using Rb: 50 + M[100 + [Rb]] = 50 + M[250] = 50 + 213 = 263 100 is an immediate address: 50 + 100 = 150 Memory System

49. Properties of address:Method of Representing Address • Full Address LDA X (EFA=X; AC<-M[X]) • Requires the largest number of bits(instruction becomes long) • Abbreviated Address LDA X (EFA=[R]+X; AC<-M[[R]+X]) • Fewer number of bits for an address(X), but uses a register • Usually, part of an address is in a register which is implied • Register includes Base Address, Page Address, Segment Address, ... • Implied Address ADD X( ACis implied) • No space(bit) at all(instruction becomes short) when there is a unique operand register • Accumulator in 1-address machines • Stack(top) in 0-address machines • Immediate Address ADD X (AC<-X) • No instruction bits for address, but for operand(instruction becomes long) • Large number of instruction bits Memory System

50. 1236 register +24 1260 operand address 24 is shorter than 1260 Abbreviating/Implying Address • Implying Address • When the desired operand is stored in a unique special register • AC, Stack • Abbreviating Address • When the desired operand is stored in the adjacent to the address stored in the special address registers • Address in the instruction needs to be specified only a few least significant bits, remainder of address is stored in a special address register; • PC • Base Address Register • Index Register • Page/Segment Address Register Memory System