ECE 445 – Computer Organization

1. Pipelined Datapath and Control (Lecture #13) ECE 445 – Computer Organization The slides included herein were taken from the materials accompanying Computer Organization and Design, 4th Edition, by Patterson and Hennessey, and were used with permission from Morgan Kaufmann Publishers.

2. ECE 445 - Computer Organization Material to be covered ... Chapter 4: Sections 5 – 9, 13 – 14

3. ECE 445 - Computer Organization Performance of the Single-Cycle MIPS

4. ECE 445 - Computer Organization

5. ECE 445 - Computer Organization Example: MIPS Clock Rate Determine the clock rate for the MIPS architecture, assuming the following: The MIPS is a Single Cycle Machine 1 clock cycle per instruction CPI = 1 Access time for memory units = 200 ps Operation time for ALU and adders = 100 ps Access time for register file = 50 ps

6. ECE 445 - Computer Organization Example: MIPS Clock Rate

7. ECE 445 - Computer Organization Example: MIPS Clock Rate

8. ECE 445 - Computer Organization Example: MIPS Clock Rate The clock cycle time for a machine with a single clock cycle per instruction will be determined by the longest instruction. In this example, the load word instruction requires 600 ps. The clock rate is then Clock rate = 1 / Clock Cycle Time Clock rate = 1 / 600 ps = 1.67 GHz

9. ECE 445 - Computer Organization Performance Issues Longest delay determines clock period Critical path: load word (lw) instruction Instruction memory  register file  ALU  data memory  register file Not feasible to vary clock period for different instructions Violates design principle Making the common case fast Improve performance by pipelining

10. ECE 445 - Computer Organization How does pipelining work?

11. ECE 445 - Computer Organization Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance §4.5 An Overview of Pipelining • Four loads: • Speedup= 8/3.5 = 2.3 • Non-stop: • Speedup= 2n/0.5n + 1.5 ≈ 4= number of stages

12. ECE 445 - Computer Organization Objective: Keep all stages of the pipeline busy at all times.

13. ECE 445 - Computer Organization Pipelining: Improving Performance Assuming all stages of pipeline are busy at all times. Length of time for each load does not change. Latency = time from start of one load to the end of same load. Maximum Throughput = # of loads completed per hour.

14. ECE 445 - Computer Organization Pipelining: Improving Performance Pipelining improves performance by increasing instruction throughput, rather than decreasing execution time of an individual instruction.

15. ECE 445 - Computer Organization The MIPS Pipeline

16. ECE 445 - Computer Organization MIPS Pipeline Five stages, one step per stage IF : Instruction fetch from memory ID : Instruction decode & register read EX : Execute operation or calculate address MEM : Access memory operand WB : Write result back to register

17. ECE 445 - Computer Organization MIPS Pipeline

18. ECE 445 - Computer Organization Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath

19. ECE 445 - Computer Organization Pipeline Performance Single-cycle (Tc= 800ps) Why is the clock period 800ps? Pipelined (Tc= 200ps) Why is the clock period 200ps?

20. ECE 445 - Computer Organization Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructionspipelined= Time between instructionsnonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease

21. ECE 445 - Computer Organization Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing Can calculate address in 3rd stage, access memory in 4th stage Alignment of memory operands i.e. on word boundaries Memory access takes only one cycle

22. ECE 445 - Computer Organization Pipeline Summary Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Subject to hazards Structure, data, control Instruction set design affects complexity of pipeline implementation The BIG Picture hazards will be discussed in upcoming lectures

23. ECE 445 - Computer Organization MIPS Pipelined Datapath §4.6 Pipelined Datapath and Control

24. ECE 445 - Computer Organization Pipeline registers Need registers between stages To hold information produced in previous cycle Why?

25. ECE 445 - Computer Organization Pipeline Operation Cycle-by-cycle flow of instructions through the pipelined datapath “Single-clock-cycle” pipeline diagram Shows pipeline usage in a single cycle Highlight resources used “Multi-clock-cycle” diagram Graph of operation over time We’ll look at “single-clock-cycle” diagrams for load word and store word.

26. ECE 445 - Computer Organization IF for Load, Store, …

27. ECE 445 - Computer Organization ID for Load, Store, …

28. ECE 445 - Computer Organization EX for Load

29. ECE 445 - Computer Organization MEM for Load

30. ECE 445 - Computer Organization WB for Load Wrongregisternumber Why?

31. ECE 445 - Computer Organization Corrected Datapath for Load

32. ECE 445 - Computer Organization EX for Store

33. ECE 445 - Computer Organization MEM for Store

34. ECE 445 - Computer Organization WB for Store

35. ECE 445 - Computer Organization Multi-Cycle Pipeline Diagram Form showing resource usage

36. ECE 445 - Computer Organization Multi-Cycle Pipeline Diagram Traditional form

37. ECE 445 - Computer Organization Single-Cycle Pipeline Diagram State of pipeline in a given cycle

38. ECE 445 - Computer Organization Questions?