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Match and Replace – A Functional ECO Engine for Multi-Error Circuit Rectification

Match and Replace – A Functional ECO Engine for Multi-Error Circuit Rectification. Speaker: Ching -Yi Huang Date : 2011/12/23 Shao-Lun Huang Wei- Hsun Lin Chung-Yang ( Ric ) Huang. Design Verification Lab Dept. EE/ Graduate Institute of Electronics Engineering

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Match and Replace – A Functional ECO Engine for Multi-Error Circuit Rectification

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  1. Match and Replace – A Functional ECO Engine for Multi-Error Circuit Rectification Speaker: Ching-Yi Huang Date: 2011/12/23 Shao-Lun Huang Wei-Hsun Lin Chung-Yang (Ric) Huang Design Verification Lab Dept. EE/ Graduate Institute of Electronics Engineering National Taiwan University, Taiwan

  2. Outline • Introduction to ECO problem • Motivation & Contribution • Definition • Rectification Pairs • Algorithm • Rectification Pair Identification • Rectification Pair Selection • Patch Minimization • Experimental Results • Conclusions

  3. VLSI Design Flow • New RTL Design Change Specification • Fixed Design • Golden Gate Netlist • Patch Front End Functional ECO Back End Functional & Timing ECO

  4. ECO Problems • ECO problems • Timing ECO: • Meet timing requirement • Buffer Insertion, Gate Sizing, … • Functional ECO: • Handle functional changes • Gate-Level Diff Minimization, Spare Cell Selection, … • Gate-Level Difference Minimization • Minimize netlist difference between the original netlist and the golden specification.

  5. Gate-Level Difference Minimization • Original netlist • Optimized / Placed netlist • Golden netlist • Golden netlist with spec. changes or bug fixes • Objective • Realize new spec. through patching original netlist. • Minimize additional patch netlist.

  6. Synthesis-based ECO rectification node Original Golden • Identify a rectification node in original netlist. • Re-synthesize this node. • Pros. • Does not depend on structural similarity. • Cons. • Patches are large and unpredictable. • Difficult to diagnose rectification nodes.

  7. Sweeping-based ECO [1] Output-side match Patch Input-side match Original Golden [1] S. Krishnaswamy, et al, “DeltaSyn: an efficient logic difference optimizerfor ECO synthesis”,ICCAD’09 • Match equivalence netlist • Replace non-equivalent netlist • Pros. • Functional corrections are often small and local change. • Input-side matching is mature (FRAIG, SAT-sweeping). • How to perform quality output-side matching?

  8. BackwardBoolean Matching • P-equivalent • F=ab+c • G = p + qr

  9. Contribution [2] C.-F. Lai, J.-H.R Jing, and K.-H, Wang, “BooM: A Decision Procedure for Boolean Matching with Abstraction and Dynamic Learning”,DAC’10 • Matching phase:rectification pair identification • Locate output-side matching boundaries. • Cut matching for ECO engine(extended [2]) • Replacement phase: rectification pair selection • Multi-error rectification • SAT-based patch selector

  10. Outline • Introduction to ECO problem • Motivation & Contribution • Definition • Rectification Pairs • Algorithm • Rectification Pair Identification • Rectification Pair Selection • Patch Minimization • Experimental Results • Conclusions

  11. Definition: Rectification Pairs Rectification Pair: {(h, i)}, {(f, c)} A group of pairs in two netlists. Replacing all no by ng makes revised netlist functionally equivalent to golden.

  12. Match-and-Replace ECO Engine

  13. An Example of Match & Replace ECO Original Golden Patch size =0

  14. Outline • Introduction to ECO problem • Motivation & Contribution • Definition • Rectification Pair • Algorithm • Rectification Pair Identification • Rectification Pair Selection • Patch Minimization • Experimental Results • Conclusions

  15. Rectification Pair Identification Rectification Pairs: (po1, po1’) (po2, po2’)…. (cut1, cut1’) (cut2, cut2’)… candidates Cut Matching match cut Original Golden 1: Push all PO pairs into RectifyPairs 2: FOR_EACH pair (p, p’) in RectifyPairs 3: CutPairCutMatching(p, p’); 4: IF( CutPair !=empty ) 5: Push all match pairs into RectifyPairs

  16. Rectification Pair Identification (1/4) Rectification Pair: (k, k)(l, l) (b, b) (c, g2) Match on (k, k)

  17. Rectification Pair Identification (2/4) Rectification Pair: (k, k)(l, l)(c, g2) (f1, f2) (g1, c) (e, e)

  18. Rectification Pair Identification (3/4) Rectification Pair: (k, k)(l, l)(c, g2)(g1, c)

  19. Rectification Pair Identification (4/4) Rectification Pair: (k, k)(l, l)(c, g2)(g1, c)

  20. Cut Matching Algorithm Sum <= 1 Sum >= 1 candidates Sum == 1 cut a1 a2 a3 . . . am 1 Cut nodes New candidates Original Golden b1 b2 b3 b4 . . . . . bn Candidate nodes BooM (DAC’10)[2] P-equivalent M-input cut nodes in original N candidates in golden M-by-N Matrix + Equivalence Checking Original Golden

  21. Rectification Pair Selection • Determine a set of rectification pairs for repairing original netlist • Many rectification pairs are dominated. • Rectification Pair Selector • An incremental equivalence checker • Miter + 2-input MUXs

  22. Rectification Pair Selector 1: Insert MUX gates 2: Assign all Control Signal 1 4: FOR_EACH MUX gate 4: Assign Control Signal 0 5: IFPair Selector is SAT 6: Assign Control Signal 1 7: FOR_EACHControl Signal 8: IF( Signal ==1 ) Replace 1 0 1 1

  23. Decision Order • Finding optimal solution is NP-hard • Structural Heuristic • The later pairs dominate the former pairs • Breadth-first searching from POs to PIs

  24. Patch Minimization • Map useless gates locally • If small wire reconnect is acceptable

  25. Further Improvements on he Patch Size 1. Merging equivalent signals 2. Reiterating M&R ECO process

  26. Outline • Introduce to ECO problem • Motivation & Contribution • Definition • Rectification Pair • Algorithm • Rectification Pair Identification • Rectification Pair Selection • Patch Minimization • Experimental Results • Conclusions

  27. Exp 1: Cube Modification • Wu et.al., "A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques," ICCAD.10. • MiniSAT SAT engine • Linux workstation with 32GB RAM and 2.5GHx Intel Xeon CPU • 42 testcases from ISCAS’89 benchmarks

  28. Exp 1: Cube Modification

  29. Exp 2: Structural Changes Swapping two nodes(NS) Inserting inverters(INV) Changing gate types(TC) Replace functions(FR)

  30. Exp 2: Structural Changes

  31. Exp 3: Further Improvement

  32. Conclusions • M&R ECO • more flexible and more efficient. • smaller patches in experiments. • Rectification pair matching algorithm • identify functional relations between netlists. • Patch selector • determine patches for multi-error rectification.

  33. Thanks For Your Attention

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