Understanding Shift Registers in Digital Electronics

1. EET202/3 DIGITAL ELECTRONICS II CHAPTER 1: SHIFT REGISTER

2. SHIFT REGISTER • Basic shift register function • Serial in / serial out shift registers • Serial in / parallel out shift registers • Parallel in / serial out shift registers • Parallel in / parallel out shift registers • Bidirectional shift registers • Shift register applications

3. SEQUENTIAL LOGIC CIRCUITS Combinational outputs Memory outputs Combinational logic Memory elements Sequential circuit Inputs Sequential circuit = Combinational logic + Memory Elements Current State of a Sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

4. REGISTER • A register is a memory device that can be used to store more than one-bit information • A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register • The storage capacity of a register is the total number of bits (1s and 0s) of digital data it can retain. • Each stage (FF) in a shift register represents one-bit of storage capacity. • The number of stages (FFs) in a register determines its storage capacity.

5. 74LS175 CLK CLR 1D 1Q /1Q 2D 2Q /2Q 3D 3Q /3Q 4D 4Q /4Q • An n-bit register is a collection of n D flip-flops with a common clock used to store nrelated bits. Example: 74LS175 4-bit register

6. Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 RSI 0 1 1 1 0 1 1 1 LSI Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 RSI 0 1 1 1 1 1 LSI SHIFT REGISTERS • Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) • Shift Left is towards MSB • Shift Right is towards LSB

7. Basic Shift Registers Functions • Consist of an arrangement of flip-flops • Flip-flop as a storage element. • Important in applications involving storage and transfer of data (data movement) in digital system • Used for storing and shifting data (1s and 0s) entered into it from an external source and possesses no characteristic internal sequence of states. • D flip-flops are use to store and move data.

8. The Flip-flop as a Storage Element • Still remember the truth table for D flip flop?

9. Concept of Storing a 1 or a 0 in a D-FF • When a 1 is on D, Q becomes 1 at triggering edge of CLK or remains a 1 if already in the SET state • When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

10. Types of Shift Register • Serial In / Serial Out Shift Registers (SISO) • Serial In /Parallel Out Shift Registers (SIPO) • Parallel In / Serial Out Shift Registers (PISO) • Parallel In / Parallel Out Shift Registers (PIPO)

11. Basic Data Movement in Shift Reg. (Four bits are used for illustration. The bits move in the direction of the arrows.)

12. SERIN D Q CLK CLOCK D Q CLK · SRG n · > · SI SO SEROUT D Q CLK Serial In Serial Out Shift Register (SISO) CLOCK SERIN SEROUT For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: Serial in: 1 0 1 1 0 0 1 1 1 0 Serial out: - - - - 1 0 1 1 0 0 Clock: ** Shift left / right

13. SISO (4-bit) Serial data input: 1010 (start with LSB) Register initially clear: 0000

15. SISO (4-bit) To get the data out of register, the bits must be shifted serially, taken off from Q3

17. SISO (4-bit)

18. SISO (5-bit) Question After 5 CLK, what is the data for each output? Answer Q4Q3Q2Q1Q0 = 11010

19. Let’s solve a few problem !!!

20. Exercise (MTE 2013/2014)

21. Solution A 7 8 1010 0111 1000 LSB

22. Solution

23. SRG n > SERIAL IN 1Q D Q CLK SI 1Q CLOCK 2Q · · · 2Q D Q CLK nQ · · · nQ D Q CLK Serial In Parallel Out Shift Register (SIPO) CLOCK SERIN PO Serial to Parallel Converter Example: 4-bit shift register Serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock: PARALLEL OUT

24. SERIN D Q CLK SERIN 1Q D Q CLK CLOCK CLOCK D Q CLK 2Q D Q CLK · · · · · · SEROUT D Q CLK nQ D Q CLK Can u see the difference? The output of each stage is available simultaneously The output is on a bit-by-bit basis

25. SIPO (4-bit) • Data bits entered serially (right-most bit first) • Difference from SISO is the way data bits are taken out of the register – in parallel. • Output of each stage is available simultaneously

26. Example :The states of 4-bit register (SRG 4) for the data input and clocks waveforms. Assume the register initially contains all 1s Question After 4 CLK, what is the data for each output? Answer Q3Q2Q1Q0 = 0110

28. Exercise (MTE 2013/2014)

29. Exercise (MTE 2012/2013)

30. Parallel In Serial Out Shift Register (PISO) • Parallel data inputs are entered simultaneously into their respective stages (FFs). • Serial output will be taken out once the data are completely stored in the register. • SHIFT/LOAD* control signal • Allow data to load in parallel into register (Parallel loading) • Shift data

31. 4-bit PISO • When signal = 1, • SHIFT When signal = 0,  LOAD • OR gate: • Allow either normal shifting operation or parallel loading operation • Depends which AND gates are enabled

32. 4-bit PISO • When signal = 0, • LOAD G1, G2, G3 enabled Allow each data bit D0, D1, D2, D3 to be applied to D input of its respective FF  parallel loading

33. 4-bit PISO • When signal = 1, • SHIFT G4, G5, G6 enabled Allow data bits to shift right from one stage to the next stage.

34. 4-bit PISO

35. Can you try and trace the output for each FF stage until you get Q3?

36. 4-bit PISO shift DATA OUT **new value always 1

37. Example: 1 0 1 0 Assume that the signal has values 011011 for 6 respective clock cycle For the parallel data input Assume: D0 = 1, D1 = 0, D2 = 1, D3 = 0

38. 0 1 1 1 0 0 0 CLK 1, Signal = 0 G1 – G3 Will get value = 1 G4 – G6 Will get value = 0 Referring to the AND gate theory, All gates that receives “0” values at shift/load can be ignored.

39. 1 1 0 1 1 1 0 Now, AND the shift/load with respective Data bit, D0 – D3

40. 1 0 0 0 1 1 1 CLK 2, Signal = 1 G1 – G3 Will get value = 0 G4 – G6 Will get value = 1 Referring to the AND gate theory, All gates that receives “0” values at shift/load can be ignored.

41. 1 1 1 1 0 1 0 Now, AND the shift/load value with Respective data that goes into G4, G5, G6

42. How do you put it in table? SHIFT/LOAD* = 011011 For the parallel data input Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0 ** The new value always 1

43. Exercise (MTE 2013/2014)

45. Parallel In Parallel Out Shift Register (PIPO) • Immediately following simultaneous entry of all data bits, the bits appear on parallel output.

46. PIPO

47. PIPO LOAD/SHIFT* = 1 : Parallel inputs are loaded synchronously on positive transition LOAD/SHIFT* = 0 : Stored data will be shifted right (QA to QD) synchronously with clock.

48. Bi-Directional Shift Registers • Data can be shifted left • Data can be shifted right • A parallel load maybe possible • Can be implemented by using gating logic that enables the transfer of a data bit from one stage to the next stage; to the right or to the left. • 74HC194 is a bidirectional universal shift register

49. Example • Determine the state of the register after each clock pulse for the RIGHT/LEFT control waveform given. HIGH enables shift right and LOW enables shift left. The register is initially storing the decimal number forty two. There is a LOW on the data-input line. 0 1 1 1 0 0 1 0 1 1 0 0

50. Example 4 2 **SRG 8 = data out at 8 clk cycle data out = 0 data out = 0 data out = 0 data out = 0 data out = 0