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CONTROL BOARD Timing and ECS upgrade for LHCb ECAL Crate

CONTROL BOARD Timing and ECS upgrade for LHCb ECAL Crate. Cyril Drancourt. Current backplane bus. ECAL Crate. TTC bus : 9 LVDs Line - CROC to all board (FE or TVB) -. CROC SLOT. FPGA_Glue (FE or TVB). FPGA_Glue (FE or TVB). FPGA_Glue (FE or TVB). Current backplane bus.

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CONTROL BOARD Timing and ECS upgrade for LHCb ECAL Crate

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  1. CONTROL BOARDTiming and ECS upgrade for LHCb ECAL Crate Cyril Drancourt

  2. Currentbackplane bus ECAL Crate TTC bus : 9 LVDs Line - CROC to all board (FE or TVB) - CROC SLOT FPGA_Glue (FE or TVB) FPGA_Glue (FE or TVB) FPGA_Glue (FE or TVB) Control Board

  3. Currentbackplane bus ECAL Crate TTC bus : 9 LVDs Line - CROC to all board (FE or TVB) - LVDS Board Signals TTL TTC ch0 Backplane Bus L0_out (unused in TVB) TTC ch1 Calib (unused in TVB) TTC ch2 Test_seq (for spy memory) FPGA_Glue (FE or TVB) Bcid_Reset TTC ch8 Control Board

  4. Needs for Upgrade LVDS TTL L0_out (unused in TVB) ? Calib (unused in TVB) Test_seq (for spy memory) FPGA_Glue (FE or TVB) Bcid_Reset Control Board

  5. Currentbackplane bus ECAL Crate SPECS bus :5 LVDs Line - 3 CROC-out, 1 CROC-in, 1 CROCinout - CROC SLOT FPGA_Glue (FE or TVB) FPGA_Glue (FE or TVB) FPGA_Glue (FE or TVB) Control Board

  6. Current TVB used SPECS bus :5 LVDs Line - 3 CROC-out, 1 CROC-in, 1 CROCinout - FPGA_Glue (TVB) LVDS TTL Board Signals RST HCAL fpga I2C bus SDA Backplane Bus SDA SDA SDA SDA SDA SCL SCL SCL SCL SCL SCL EPPI fpga I2C bus SDA Delay-chip I2C bus DIR GOLs A I2C bus SCL GOLs B I2C bus Control Board

  7. Needs for Upgrade FPGA_Glue (TVB) LVDS TTL Board Signals HCAL fpga I2C bus Backplane Bus SDA SDA SDA SDA SDA SCL SCL SCL SCL SCL EPPI fpga I2C bus Delay-chip I2C bus GOLs A I2C bus GOLs B I2C bus Control Board

  8. Currentbackplaneclock ECAL Crate 1 LVDS Point to Point- CROC to each board (FE or TVB) - CROC SLOT (FE or TVB) Control Board

  9. Current TVB clock 1 LVDS Point to Point- CROC to each board (FE or TVB) - • Need to keep for upgrade Board inside (TVB) repeater Backplane side DelayChip (TVB) FPGA_Glue (TVB) Control Board

  10. CurrentbackplaneSpare ECAL Crate 4 LVDS Point to Point- CROC to each TVB - CROC SLOT (TVB) CLK SD1 Deserializer SD2 EPPI FPGA SD3 • LVDS Spare line Cannot use for upgrade Control Board

  11. TFC+ECSInterface to FE GBT link for upgrade Clock[7:0] External clock reference FEModule E – Port Phase - Shifter CLK Reference/PLL E – Port FEModule E – Port E – Port DEC/DSCR CDR Phase – Aligners + Ser/Des for E – Ports 80, 160 and 320 Mb/s ports CLK Manager SCR/ENC SER E – Port FEModule E – Port E – Port One 80 Mb/s port Control Logic Configuration GBT – SCA JTAG I2C Slave I2C Master E – Port I2C (light) Control Board

  12. TFC+ECSInterface to FE ECAL crate application Clock[7:0] Control Board with GBT chip FEB GBT- SCA E – Port Phase - Shifter CLK Reference/PLL E – Port FEB GBT- SCA E – Port E – Port DEC/DSCR CDR ECAL Crate Backplane Phase – Aligners + Ser/Des for E – Ports CLK Manager Not enougt line ressource in current ECAL Crate Backplane….! Because all e-link are point to point (not a bus) SCR/ENC SER E – Port FEB GBT- SCA E – Port E – Port Control Logic Configuration TVB Glue- SCA JTAG I2C Slave I2C Master E – Port Control Board

  13. TFC+ECSInterface to FE ECAL crate application Clock[17:0] Control Board with GBT chip FEB Glue- FPGA LVDS>TTL TFC decoding FEB Glue- FPGA GBT LVDS>TTL e-link i2c FPGA conv GBT SCA TTC bus I/O ECAL Crate Backplane SPECS bus FEB Glue- FPGA What about news ECS mezzanine study to replace SPECS mezzanine ? LVDS>TTL TVB Glue- FPGA LVDS>TTL Control Board

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