Parallel Port

1. Parallel Port • IEEE Std. 1284-1994 Standard Signaling Method for a Bi-direction Parallel Peripheral Interface • for Personal Computer. The standard defines 5 modes: • Forward direction only • Compatibility Mode ( Standard Mode ) • Reverse direction only • Nibble Mode • 4 bits at a time using status lines for data • Byte Mode • 8 bits at a time using data lines, sometimes referred to as a “bi-directional” port • Bi-directional • EPP • Enhanced Parallel Port- used primarily by non-printer peripheral, CD ROM, tape, • hard drive, network adapter, etc... • ECP • Extended Capability Port- used primarily by new generation of printers and scanners

2. Parallel Port Signals OUT: STROBE#, SELECTIN#, AUTOFD#, INIT# IN : BUSY, ACK#, PERROR, FAULT#, SECLECT I/O : PD [7:0]

3. Compatibility Mode 1.Host assert SELECTIN#, device assert SELECT to acknowledge that it’s selected 2.Host assert INIT# to initialize the device, if error, device may assert FAULT# or PERROR. Data Valid PD[7:0] BUSY STROBE# ACK# Interrupt or software polling

4. SPP register • at least 4 I/O instructions for one byte data output • hand shaking by software • can use a FIFO buffer with this mode • ( Parallel Port FIFO mode )

5. Nibble Mode HostBusy PtrClk DataAvail# XFlag AckDataReq PtrBusy BITS 1-4 BITS 5-8 1.Host signals ability to take data by asserting HostBusy low 2.Peripheral responds by placing first nibble on status lines 3.Peripheral signals valid nibble by asserting PtrClk low 4.Host sets HostBusy high to indicate that it has received the nibble and isn’t yet ready for another nibble 5.Peripheral sets PtrClk high to acknowledge the host 6.States 1 through 5 repeat for the second nibble

6. Byte Mode HostBusy PtrClk PD[7:0] Data Valid HostClk 1.Host signals ability to take data by asserting HostBusy low 2.Peripheral responds by placing first byte on data lines 3.Peripheral signals valid byte by asserting PtrClk low 4.Host sets HostBusy high to indicate that it has received the byte and isn’t yet ready for another byte 5.Peripheral sets PtrClk high to acknowledge the host. Host pulses HostClk as an acknowledgement to the peripheral 6.States 1 through 5 repeat for additional bytes

7. EPP The EPP protocol provides four types of data transfer cycles: 1. Data Write Cycle 2. Data Read Cycle 3. Address Write Cycle 4. Address Read Cycle

8. EPP Registers 1. Transfer within one ISA I/O cycle 2. Handshaking by hardware 3. Can be expand to 32 bits 4. Intermixing or read and write

9. EPP Mode Write Cycle

10. EPP Mode Read Cycle

11. ECP • The ECP protocol provides 2 cycle types in both the forward and reverse directions • 1. Data Cycles • 2. Command Cycles • Run Length Count • Channel Address

12. ECP Register Definitions

13. ECP features • 1. Run Length Encoding ( RLE ) data compression • enable real time data compression that can achieve compression ratio up to 64:1 • 2. Channel Addressing • used to address multiple logical devices within a single physical device • 3. DMA enable • 4. FIFO for both device • 5. Changes in the data direction must be negotiated • ( different with EPP )

14. ECP Forward Data & Command Cycle Forward Transfer phase transitions: 1.The host places data on the data lines and indicates a data cycle by setting HostAck high. 2.Host asserts HostClk low to indicate valid data 3.Peripheral acknowledges host by setting PeriphAck high 4.Host sets HostClk high. This is the edge that should be used to clock the data in to the peripheral. 5.Peripheral sets PeriphAck low to indicate that it is ready for the next byte. 6.The cycle repeats, but this time it is a command cycle because HostAck is low.

15. ECP Reverse Data & Command Cycle 1.The host requests a reverse channel transfer by setting nReverseRequest low. 2.The peripheral signals that it is OK to proceed by setting nAckReverse low 3.The peripheral places data on the data lines and indicates a data cycle by setting PeriphAck high. 4.Peripheral asserts PeriphClk low to indicate valid data 5.Host acknowledges by setting HostAck high 6.Peripheral sets PeriphClk high. This is the edge that should be used to clock the data in to the host. 7.Host sets HostAck low to indicate that it is ready for the next byte. 8.The cycle repeats, but this time it is a command cycle because PeriphAck is low.

16. Negotiation Negotiation phases transitions: 1.The host places the requested extensibility byte on the data lines 2.The host then sets nSelectIn high and nAutoFeed low to indicate a negotiation sequence. 3.A 1284 peripheral will respond by setting nAck low, and nError,PE and Select high. A non-1284 peripheral will not respond. 4.The host sets nStrobe low. This is used to strobe the Extensibility byte in to the peripheral. 5.The host then sets nStrobe and nAutoFeed high to signal to the peripheral that it recognizes it as a 1284 device. 6. The peripheral responds by setting PE low, nError low if the peripheral has reverse channel data available, and Select high if the requested mode is available, or Select low if the requested mode is not available. 7.The peripheral now sets nAck high to signal that the negotiation sequence is over and the signal lines are in a state compatible with the request mode.

17. Extensibility Byte Bit Values