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Nanometer Scale CMOS Threshold Logic Gates

United Arab Emirates University College of Engineering Project Code EEF2-4. Nanometer Scale CMOS Threshold Logic Gates. Supervised by: Dr. Mawahib Sulieman Presented by: Ameena Al- Sumaiti 200105247 Durrea Abbad Durra 200104834 Rauda Al- Amri 200217846

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Nanometer Scale CMOS Threshold Logic Gates

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  1. United Arab Emirates University College of Engineering Project Code EEF2-4 • Nanometer Scale CMOS Threshold Logic • Gates Supervised by: Dr. MawahibSulieman Presented by: Ameena Al-Sumaiti 200105247 DurreaAbbad Durra 200104834 Rauda Al-Amri 200217846 SuaadAl-Ateeshi200202766 1

  2. Outline: • History and definition of threshold logic • Threshold logic gate design implementation options • Gate design method & characterization • Full adder circuit • Carry look-ahead adder circuit • Results • Project impacts 2

  3. IEEE Journal of solid state circuits-1996 “ Threshold logic emerged in the early 1960s as unified theory of logic gates“ 3

  4. Threshold logic gate represents a digital summation. Operation of Threshlod Logic Gate: - Inputs: binary variables - Outputs: binary variables Threshold logic gate operation is described by: Threshold Logic Gate 4

  5. Threshold Logic Gate Design Options: • Capacitor Threshold Logic Gate B) Conductance Threshold Logic Gate 5

  6. A) Capacitor Threshold Logic Gate: Vref: Reference voltage, ΦR: Reset phase, ΦE : Evaluation phase 6

  7. B) Conductance Threshold Logic Gate: • Output-wired inverters • Lerch 1973: • Same weight • Different weights 7

  8. Decision: • The output wired inverters was chosen. • The reason: • Its simple design and fast performance. • Floating gate in Neuron MOS transistor (latest version of capacitive implementation), which is difficult to deal with in designing. 8

  9. Gate Design Method: • Select the widths of the inverters transistors based on the channel length from the predictive technology models. • Write the threshold function from the Boolean function by finding the threshold value. • Study possible cases of different inputs and focus on the critical ones: above and below the threshold. 9

  10. Gate Design Method: • Calculate the resistances (RPMOS & RNOMS) and the corresponding output voltage. • Select the appropriate value of KR and calculate the width of the buffer transistor 10

  11. Example: OR Gate Design Parameters From The Predictive Technology Models 11

  12. 2. OR Gate Threshold Function 12

  13. 2. OR Gate Threshold Function 13

  14. 3. Possible Cases for OR Resistor Level Implementation Case 1: a and b = 0 Case 2: a and b = 1 Case 3: a ≠ b VGB VGB VGB 14

  15. 5. Selecting KR 4. R triode Calculation Where, µ: Mobility of the carriers Cox: Capacitance of gate oxide W: Width of the transistor L: Length of the transistor VGS: Gate Source Voltage Vth: Threshold voltage To achieve the right value of KR, VGB1 should be > VIH and VGB2 < VIL . 15

  16. NMOS parameters calculated for L = 90nm, 65nm and 45nm PMOS parameters calculated for L = 90nm, 65nm and 45nm 16

  17. VIH and VIL calculated for L = 90nm, 65nm and 45nm 17

  18. OR Gate Design: Parameters considered for L = 90nm, 65nm and 45nm: 18

  19. Characteristics of the OR Gate of L= 90nm, 65nm and 45nm: • OR gate power dissipation • Using WinSpice program: • There is no power dissipation problem when moving to smaller technologies, because no leakage current is significantly affecting. 19

  20. 2. OR Gate Propagation Delay: • The propagation delay is defined as the time difference between 50% of the input to 50% of the output. • As the technology gets smaller the delay increases. 20

  21. Threshold Logic Gates Designs: • Following the same procedure of designing OR gate the following designs were achieved: 21

  22. Full Adder • The adder is composed of two main parts that are the sum and the carry. • Full adder can be implemented using both the majority gate and the 1 1 1 2 gate. • The majority gate is used to determine the output carry; while the sum is implanted as 1 1 1 2 gate. S = a + b + Ci + 2Co - 2.5 Co = a + b + Ci - 1.5 22

  23. FASTER Carry Look-ahead Adder • It is made of 4 classes of blocks: • Generate: AND operation • Propagate: OR operation • 1 1 2: GK + PK . GK-1 • 1 1 1 2: S’ = (a’ . Co)+(b’ . Co)+(Ci. Co)+(a’ . b’ . Ci’) 23

  24. Results: 24

  25. Project Impacts • This project is a new trend since it deals with nano-meter scales. • The project was not associated with any environmental issues as the gates were not implemented in the laboratory. • No safety considerations were considered while working on this project as its main domain was in the field of computer modeling and analysis. • The cost of the project was $368 as it costs to buy Win Spice simulation tool $92/member. No other costs were associated with the project. 25

  26. Conclusion: • Many theoretical results show that threshold logic circuits are more powerful and efficient than classical Boolean circuits. • This project is basic point where other complex projects can be implemented using the library of gates designed, simulated and characterized. • Our library contains: majority gate, 1 1 2 gate, AND gate, OR gate, 1 1 1 2 gate, full adder and carry look-ahead adder. 26

  27. Conclusion: • All the components of the WinSpice library were designed and characterized at the nanometer scale in terms of delay and power dissipation. • The nano-meter scale threshold logic gates project can be further expanded by implementing more complex circuits. 27

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