CISC vs RISC

1. CISC vs RISC

2. Y86 • Y86 Instruction Set Architecture • Similar state and instructions as IA32 • Simpler encodings • Somewhere between CISC and RISC

3. CISC • CISC (pronounced “sisk”) • Complex Instruction Set Computer • Dominant style through mid-80’s • Stack-oriented instruction set • Use stack to pass arguments, save program counter • Explicit push and pop instructions

4. CISC • Arithmetic instructions can access memory • addl %eax, 12(%ebx,%ecx,4) • requires memory read and write • Complex address calculation • Condition codes • Set as side effect of arithmetic and logical instructions

5. CISC • Philosophy • Add instructions to perform “typical” programming tasks

6. RISC • RISC (pronounced “risk”) • Philosophy • generate efficient code for a much simpler form of instruction set • Why not CISC ? • high-level instructions were very difficult to generate with a compiler and were seldom used

8. CISC vs. RISC CISC RISC Variable-length encodings. IA32 instructions can range from 1 to 15 bytes. Fixed-length encodings. Typically all instructions are encoded as 4 bytes.

9. CISC vs. RISC CISC RISC Multiple formats for specifying operands. e.g., a memory operand specifier can have many different combinations of displacement, base and index registers, and scale factors. Simple addressing formats. Typically just base and displacement addressing.

10. CISC vs. RISC CISC RISC Arithmetic and logical operations can be applied to both memory and register operands. Arithmetic and logical operations only use register operands. Memory referencing is only allowed by load and store instructions. This convention is referred to as a load/store architecture.

11. CISC vs. RISC CISC RISC Implementation artifacts hidden from machine- level programs. The ISA provides a clean abstraction between programs and how they get executed. Implementation artifacts exposed to machine- level programs. (e.g., Some RISC machines prohibit particular instruction sequences and have jumps that do not take effect until the following instruction is executed. The compiler is given the task of optimizing performance within these constraints.)

12. CISC vs. RISC CISC RISC Condition codes. Special flags are set as a side effect of instructions and then used for conditional branch testing. No condition codes. Instead, explicit test instructions store the test results in normal registers for use in conditional evaluation.

13. CISC vs. RISC CISC RISC Stack-intensive procedure linkage. The stack is used for procedure arguments and return addresses. Register-intensive procedure linkage. Registers are used for procedure arguments and return addresses. Some procedures can thereby avoid any memory references. Typically, the processor has many more (up to 32) registers.

14. Review Y86 • Y86 ISA studies both CISC and RISC • CISC: condition codes, variable-length instructions, and stack-intensive procedure linkages • RISC: load-store architecture and a regular encoding

15. Controversy and Fuse • Original Debate • Strong opinions! • CISC proponents: easy for compiler, fewer code bytes • RISC proponents: better for optimizing compilers, can make run fast with simple chip design

16. Controversy and Fuse Neither RISC nor CISC in their purest forms were better than designs that incorporated the best ideas of both • RISC  CISC • More instructions (multiple cycles to execute) • Implementation artifacts exposed to machine-level programs

17. Controversy and Fuse Neither RISC nor CISC in their purest forms were better than designs that incorporated the best ideas of both • CISC  RISC • Dynamically translate CISC instruction into a sequence of simpler, RISC-like operations • X86-64: more register, close to register-intensive procedure linkage, …

18. CISC vs. RISC • Current Status • For desktop processors, choice of ISA not a technical issue • With enough hardware, can make anything run fast • Code compatibility more important • For embedded processors, RISC makes sense • Smaller, cheaper, less power

19. At glance of MIPS • MIPS emphasizes • A simple load-store instruction set • Design for pipelining efficiency, including a fixed instruction set encoding • Efficiency as a compiler target

20. At glance of MIPS • Registers • 32 64-bit general-purpose registers • 32 floating-point registers • The value of R0 is always 0 • Data Type • 8-, 16-, 32- and 64-bit integer data • 32-, 64-bit floating point data

21. At glance of MIPS • Addressing Modes • immediate and displacement (offset) • 16-bits fields

22. At glance of MIPS • Instruction Format • 32-btis fixed instruction • 6-bit primary opcode • I-type, R-type and J-type

23. I-type Opcode rs rt imm J-type Opcode Offset added to PC R-type Opcode rs rt rd shamt funct

24. At glance of MIPS • Operations • Load and Store I-type LD R1,30(R2) Regs[R1]  Mem[30+Regs[R2]] SD R3, 500(R4) Mem[500+Regs[R4]]  Regs[R3]

25. At glance of MIPS • Operations • Arithmetic/logical instructions R-type DADDU R1, R2, R3 Regs[R1]  Regs[R2] + Regs[R3] DADDIU R1, R2, #3 Regs[R1]  Regs[R2] + 3 DSLL R1, R2, #5 Regs[R1]  Regs[R2] << 5 SLT R1, R2, R3 Regs[R1]  (Regs[R2]<Regs[R3]) ? 1 : 0

26. At glance of MIPS • Operations • Control Flow J name PC36..63 name JAL name Regs[R31]  PC+8; PC36..63 name ((PC+4)-227) <= name <= ((PC+4)+ 227) JR R3 PC  Regs[R3] JALR R2 Regs[R31]  PC+8; PC  Regs[R3] BEQZ R4, name if (Regs[R4]==0) PC  name ((PC+4)-217) <= name <= ((PC+4)+ 217) MOVZ R1,R2,R3 if (Regs[R3]==0) Regs[R1]  Regs[R2] J-type I-type R-type

27. Thanks