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-Converters

-Converters. Timo Mantere University of Vaasa Department of Electrical Engineering and Automation P.O. Box 700, FIN-65101 Vaasa, Finland timan@uwasa.fi. Outline. Introduction to Analog-to-digital conversion Why? How? What are the problems? Delta-sigma conversion What? Why? How?.

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-Converters

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  1. ΔΣ-Converters ™ -Converters Timo Mantere University of Vaasa Department of Electrical Engineering and Automation P.O. Box 700, FIN-65101 Vaasa, Finland timan@uwasa.fi

  2. ΔΣ-Converters ™ Outline • Introduction to Analog-to-digital conversion • Why? • How? • What are the problems? • Delta-sigma conversion • What? • Why? • How? NOTE! Due the short preparation time, many pictures in this representation is taken from the referred sources

  3. ΔΣ-Converters ™ ADC conversion • The microprocessors handle only digital information • However, most of the real world signals are analog • Therefore, the analog signals must be converted into digital by an analog-to-digital converter (ADC) in order to process them with a computer or microprocessor • The normal ADC resolution is determined by the reference voltage and by the amount of bits after the conversion • The resolution (=the smallest step size), means the smallest voltage change that can be measured with the ADC. It is calculated by dividing the reference voltage by the number of possible conversion values (2Nbits) • E.g. we have 8 bit converter (28 = 256 steps), and the reference voltage is 1v, so the step size is: 1v/28 = 3.9mV

  4. ΔΣ-Converters ™ ADC conversion • In ADC the continuous analog signal is sampled and represented as discrete time digital values (quantization) • Usually the conversion is made linearly with time (fixed sample time ts) • The conversion is usually linear; the fixed change in the input voltage causes the linear change in the output values ADC 011100101… ts

  5. ΔΣ-Converters ™ ADC types • There are several different type of ADCs, that has various speeds, uses different interfaces, and possess differing degrees of accuracy • The most common ADC types are flash, successive approximation, and sigma-delta • Other ADC types include: • A delta-encoded ADC • A Digital ramp ADC (also called integrating, dual-slope or multi-slope ADC ) • A pipeline ADC (also called subranging quantizer) • Hybrids; e.g. between flash&SAR types

  6. ΔΣ-Converters ™ The direct ADC (flash) Analog input voltage Vsignal Reference voltage Vref • A direct conversion ADC (or flash ADC) uses a linear voltage ladder with a comparator for each step to compare the input voltage to the successive reference voltages • Flash ADC is parallel, and the signal is both feed simultaneously for all of the comparators and also sampled simultaneously • Extremely fast, sampling rate up to 1GHZ • The problem is resolution, since the amount of comparators increases exponentially with bits needed, and the accuracy requires tight resistors tolerances • Flash converters are usually impractical, if the precisions requirement is more than 8 bits (255 comparators) Encoder N bit digital output 2N-1 comparators

  7. ΔΣ-Converters ™ Successive approximation ADC • The successive approximation converter uses a comparator and counting logic to perform a conversion • At the beginning of the conversion the input is compared to the half of the reference voltage Vref/2 • If input larger than Vref/2, the most significant bit (MSB) of the output is set, and the corresponding value is subtracted from the input, and the result is checked against Vref/4 • If its not, the MSB is set to 0, and input is compared against Vref/4 • This process continues until all the output bits have been either set or reset, that requires as many clock cycles as there are output bits to perform the whole conversion • If the input voltage changes during the conversion, it causes error, higher sampling rate helps to reduce that error • ADCs of this type have good resolutions and quite wide ranges. They are more complex than some other designs The picture above is taken from: http://en.wikipedia.org/wiki/ Successive_Approximation_ADC The picture below is taken from: http://hyperphysics.phy-astr.gsu.edu/ hbase/electronic/adc.html

  8. ΔΣ-Converters ™ Aliasing • If the sampling frequency fsample is less than Nyquist frequency, fN = finput/2, the original signal cannot be reconstructed • The unwanted frequencies (those > fN) are usually filtered off • If not filtered off, they cause aliasing (noise) • The frequency where the aliasing noise folds, with each input frequency (red area), can be seen from the picture below as corresponding amplitude in the green area Undersampled: fsample< max(finput/2) The original signal cannot be reconstructed Oversampled: fsample> max(finput/2) The original signal can be reconstructed Amplitude finput fN 2fN 3fN 4fN

  9. ΔΣ-Converters ™ Problems with ADC conversion • Accuracy • The accuracy of ADC conversion (bits) • Tolerance of analog components (resistors, capasitors, opamps, etc.) • Speed • High speed solutions • Aliasing • The filtering of high frequencies are problematic, the ideal lowpass filter does not exist in the real world • The major benefit of oversampling converters is that the filtering required to prevent aliases is relatively simple

  10. ΔΣ-Converters ™ The resolution and speed of ADCs Speed (sampling rate) Power bipolar GHz >W Flash CMOS Sub-Ranging Pipeline Successive Approximation Sigma-Delta Discrete <mW Ramp Hz Number of bits 18 6 Picture taken from: Francis Anghinolfi: ANALOG-TO-DIGITAL CONVERTERS, 2005 http://humanresources.web.cern.ch/HumanResources/external/training/tech/special/ELEC2005/ELEC-2005_25Jan_1.ppt

  11. ΔΣ-Converters ™ -converters • In  converters the signal is highly oversampled, therefore the filtering of high noise frequencies are not as critical as with other ADC types •  converters also enables noise shaping • Therefore, extremely high resolution can be achieved (commercial products up to 24 bits) • Resolution can be changed afterwards • Less requirements for analog components accuracy

  12. ΔΣ-Converters ™ -converters • 1st order  converter consist of summing operator (), integrator, comparator and 1-bit DAC in the feedback loop • 2nd order  consist of 1st order  and another summing operator and integrator. In simulation the first integrator is usually continuous time (non-delayed), while the second is discrete time (has unit-delay) • Nth order  is similar to 1st order , but the integrator is replaced by Nth order lowpass or bandbass filter   + - 1-bit DAC     + + - - 1-bit DAC ~ ~  ~ + - 1-bit DAC

  13. ΔΣ-Converters ™ Why use  • Mathematical’s attemp to explain: Ron DeVore, Texas Instruments Visiting Professor, University of South Carolina Analog to Digital Conversion: Why Sigma-Delta Modulation? • Digital processing of signals is preferred to analog because of its accuracy. But most signals are inherently analog and need to be converted to digital • The preferred method for A/D conversion, known as Sigma-Delta modulation, uses high oversampling and coarse quantization • Under the traditional model of bandlimited signals, this is in direct conflict with the Shannon theory which would advocate sampling at Nyquist rate • http://www.cscamm.umd.edu/programs/ocq05/devore_ocq05.htm • One of  advantages is that it is almost impervious to machine error in implementing quantization • On the other hand  methods have slow convergence compared with Pulse Code Modulation (PCM) • He describe a class of encoders that have exponential convergence of PCM while retaining the error correcting of 

  14. ΔΣ-Converters ™ Problems with -converters • High sampling rate -> requires high speed components •  converters do not perform well with multiplexed signals • In the multiplexed application have to flush the old signal out before  captures a valid data point from the new input channel. The effective sampling rate is therefore quite low

  15. ΔΣ-Converters ™ Problems with -converters •  converters do not perform well with low signal levels (close to the ground) • The DC bias may cause periodic patterns close to the ground level • General explanation for  modulators produce these unwanted patterns in order to resolve small incremental changes in the input signal • E.g. in a second-order  modulator, the single-bit output has only a limited number of patterns for representing the small input signals close to the signal ground level, and therefore patterns have a large instantaneous error. When the signal is feedback for the two previous stages the pattern noises further resonates in the modulator When signal is close to the zero level there is much more saw-effect

  16. ΔΣ-Converters ™ Noise shaping in -converters • The picture below represents how noise folds with 1.-3. order -converters • The noise in normal Nyquist ADC (yellow) folds to the whole  oversampling frequency band (blue), so it’s level is much lower • The noise in the blue area can be filtered out • The noise in the green area will stay in the measured signal • However, there is less noise is in the frequency area of interest (marked green) the higher the  order is (“noise shaping”) Image taken from: http://en.wikipedia.org/wiki/ Sigma-delta_modulation

  17. ΔΣ-Converters ™ Conversion noise in -converters • The picture below represents -conversion noise (signal-noise ratio, SNR) vs. oversampling ratio with 0.-5. order s Image taken from: http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html 0. order = delta converter 1.-5. order =  converters Every doubling of oversampling ratio increases SNR by 3dB in 0. order 9dB in 1st order (1.5 bits) 15dB in 2nd order (2.5 bits) i.e. 3dB+order*6dB

  18. ΔΣ-Converters ™ Decimation • In the normal ADC the resolution is determined by with how many bits the digital value is represented after the conversion • In  after the conversion signal is 1-bit data, this can be changed into multi-bit data by different methods • Bit counting: take n length samples from 1-bit data and count how many 1:s it has, the value representing that during that sample is 1:s/n, e.g. 10101110 -> 5/8=0.625 -> 101 • Sample rate reduces as much as how long bit word counted • Digital low pass filtering and the multi-bit value is low pass filter outcome • Usual methods use both of the above • E.g. 6.4 MHz 1-bit data -> 400 kHz 12-bit data -> 100 kHz 16-bit data Digital low-pass filtering Bit counting

  19. ΔΣ-Converters ™ Stability • 1st order  is always stabile • Higher order s become unstable if the amplitude of measured signal is close to the conversion level • The SNR of s is better, if amplitude is closer to the top level • In the normal ADC the resolution is determined by with how many bits the digital value is represented after the conversion • The unstable situation is recognized from the long sequences of 0s or 1s Higher order, better SNR, but becomes unstable earlier SNR Unstable situation, long periods of 0s or 1s 1 Amplitude

  20. ΔΣ-Converters ™ Restore stability • Stability is restored with different methods • Reset the integrators • Instant recovery, high SNR loss • Clipping the integrators (limiting integrator values) • Easy to implement, slow recovery • Activating local feedback loops • Fast recovery, • Requires complicated excess hardware (feedback loop around each integrator • Decreasing the order (short circuit high order integrators) • Fast, requires some excess hardware

  21. ΔΣ-Converters ™ Radio s Table taken from: Fang Chen: Design of continuous time band pass delta-sigma ADC for software-defined radio systems, 2005 http://cybertron.vlsi.uwindsor.ca/presentations/chen1w_seminar_2.pdf • In the research literature there is very high frequency band bass :s been generated for radio-signals ENOB=effective number of bits BW=f bandwidth FIF= IF-frequency (a sort of middle bandwidth) Fs= f sample

  22. ΔΣ-Converters ™ Commercial s • Datatranslation Table taken from: http://www.datx.co.uk/Email/Product_Guide.pdf

  23. ΔΣ-Converters ™ Some Matlab experiments with  1st order  converter • One integrator and feed-back loop 2nd order  converter • Two integrators in the feed-back loop 3rd order  converter • Only for testing purposes, not stable in this form unless integrators clipped (limited)

  24. ΔΣ-Converters ™ Experiments with 1st order  Blue: Original signal Red: Original+feedback Signal before comparator Blue: Digital signal (after comparator) Red: Lowpass filtered Blue: Original signal Red: Reconstructed

  25. ΔΣ-Converters ™ The effect of oversampling • The analog signal can be reconstructed from reconstructed  signal by lowpass filtering • The higher the oversampling ratio • The less error there is between the original signal and the reconstructed • The lower fcut/fsample ratio can be

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