FE8113 ”High Speed Data Converters”

1. FE8113 ”High Speed Data Converters”

2. Course outline • Focus on ADCs. Three main topics: • 1: Architectures • ”CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd ed., Rudy van de Plassche, Kluwer Academic Publishers, Ch. 1-3 • 2: Digital background calibration • Selected papers • 3: State-of-the-art converters • Selected papers

3. Part 1: Architectures • First three chapters of van de Plassche’s textbook • Ch.1: The Converter as a black box • Ch.2: Specifications of converters • Ch.3: High-Speed A/D Converters

4. Chapter 2Specifications of converters

5. Digital data coding TTL, CMOS, ECL Serial to parallel conversion - Data latched out by latch clock - Directly drives switches in DA-converters - Output glitches - Deglitching - Switch optimization - Accurate board layout for matched delays

6. Digital coding schemes • Offset binary code • Major carry transition for signal around zero • Glitch sensitive • Sign-magnitude code • Signal inversion around zero • Low-level linearity issues • Twos complement • Used for computational operations

7. DC specifications • Absolute accuracy • Full-scale input or output compared to the absolute standard of the National Bureau of Standards • Mostly related to the reference source • Relative accuracy • Deviation of the output signal or code from a straight line • Also called integral non-linearity (INL) • No missing codes (monotonicity): INL<±1/2LSB

8. Nonlinearity calculation • Binary w. output bit: • Full-scale value B: • Ideal step-size: • Linearity error of kth bit: • INL:

9. Nonlinearity calculation II • Monotonicity: • D/A: No increase in analog output value when input increases by a value of one LSB: • To guarantee monotonicity the sum of errors for all bits must never exceed ½ LSB level

10. Other static specifications • DNL • Quote from book: ”The difference between two adjacent analog signal values compared to the step-size (LSB-weight) of a converter generated by transitions between adjacent pairs of digital code numbers over the full range of the converter” (...) • Offset: • Non-zero output when zero input. • Temperature dependence: • For thermal mismatch below ¼ LSB: • Supply voltage variations: • Typically specified, e.g. ±5%

11. Dynamic specification • SNR • Signal power divided by integrated noise power. • Harmonics not included • If harmonics included: • SNDR: Signal to noise and distortion ratio • 6.02n+1.76 dB • SFDR • Ratio between full-scale fundamental and largest harmonic distortion component • ENOB • (SNDR-1.76)/6.02

12. Element matching vs. INL • Requirements: INL≤ ½ LSB • See book for details. • Based on measurement of many samples. • σ=mismatch standard variation.

13. ENOB and SDNR vs. INL model • Transfer-function with INL: • INL-model (differential): • Out vs. in with three coefficients in INL-model: • Gives odd harmonics: • Only one coefficient: • Resulting ENOB:

14. SFDR and IMD vs. INL model • Distortion: • Quantization component: • SFDR: • Intermodulation:

15. Glitches • Important for performance of DAC • Major carry-code transition • Modelled with square glitch with area/energy (for MSB glitch): • Compare to LSB-energy:

16. Noise • Thermal noise • No correlation with q-noise: • In a 16b DAC with 98.1dB quantization-SNR, the thermal noise must be less than -108dB for 0.5dB loss in total SNR.

17. Noise • ADC: Noise dithers the comparator in an ADC • Estimating comparator output-noise by using probability of wrong desicion: • Noise: σ = ½ LSB: • Bias quantizer ½ LSB over quantization-level:

18. Other error sources • Minimum reference step-size: • The possibility noise amplitude is bigger than kσ • Min. Reference step size should be 6-7 times greater than comparator RMS-noise • Bit-error rate • Number of desicion errors • For ADC typically 10-15 to 10-10 • Max sampling-rate • Rate where DR is decreased 3dB • Digital signal feed-through • Couple HF signals to the output

19. Other error sources • Distortion • Signal band also present at multiples of fs. • Inter-modulation products may occur when applied to analog amplifier. • Mixing fs-fin with fs+fin • Product at 2fs • Harmonic • Mixing 2(fs-fin) with fs+fin • Product at fs-3fin • Non-harmonic • Only harmonics in baseband if fs>4fin. • PSRR • Immunity no power-supply noise • Settling-time • Very important in any successive approximation ADC (internal DAC) • Aquisition-time • Track-command to response delay • Limits max fs

20. Other error sources • Aperture-time • Time-difference between hold-command and the time the sample is taken • Can give input-dependent error in sample-and-hold amplifier • Sample-and-hold step • Charge-feedthrough can give step in transition from sample-to-hold phase • Droop-rate • Discharge of hold-capacitor in hold-phase • Signal feed-through • To capacitor in hold mode • Must be attenuated 70-80dB in 8-10bit ADC • Noise in S/H-amplifier • Input-noise will be tracked • Peak-noise must be below LSB-level

21. Other error sources • Overview of S/H-specifications • Settling-time • Aquisition-time • Aperture time / jitter • S/H step • Droop rate • Hold-mode feedthrough • S/H amplifier noise

22. Other error sources • Analog system bandwidth • In an ideal converter system the maximum analog bandwidth is equal to fs/2. • ERB • Effective resolution bandwidth • Bandwidth where resolution is within -3dB of nominal. • Figure of merit: • Standard for comparison • FOM expected to drop factor 10 every 10th year

23. Discussion...