CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 11

1. W’05 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital SystemsLecture 11 February 23 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

2. Outline • Administrative Matters • Chapter 7 • Specification of Sequential Systems • State Minimization

3. Administrative Matters • Project #2 • Is posted on the web • Due on March 2 (Wednesday) • Teamwork is allowed and encouraged • Find your partner as early as possible • Homework #7 • Is posted on the web • Midterm • Will be handed back and discussed on Next Monday

4. (Hardware) Systems Analog Digital Sync. Seq. Async. Comb. Sequential Systems: Overview • Basic Concepts • Synchronous sequential systems • Clocks • States • Finite state machines • Mealy and Moore machines • Specification • Time behavior (I/O sequence) • State transition table • State diagram • Minimization

5. Definition of Sequential Systems

6. Sync. Vs. Async. Sequential Systems Synchronous Asynchronous

7. Clock • An independent periodic reference signal • Provided by • An internal crystal • An external 60 Hz alternating current • Make sure you know • When is the present (t) • When is the next (t+1) • back to the future • When is the previous (t-1) • forth to the past

8. Time t 0 1 2 ... Input xi(t) Output zi(t) Time-Behavior Specification • Behavior of a sequential system can be specified by a sequence of input(s)/output(s) pairs with respect to the clock signal

9. t 0 1 2 3 4 5 6 7 x(t) 3 5 7 8 3 6 1 2 y(t) 5 2 4 2 5 6 3 7 s(t) 8 7 1 1 9 2 5 9 c(t) 0 0 1 1 0 1 0 0 Example 7.1: Serial Decimal Adder • Addition is performed one digit at a time, starting from the LSB • Output is generated at each time instant • As a result, a 8-digit serial decimal adder needs 8 clock cycles to finish the calculation s = x + y = 21638753+73652425

10. State • Introduced to help “memorize” the complete input/output sequences • Usually number of states are finite • Itself is also a time function • Two types of states are defined: • present state (PS): s(t) • next state (NS): s(t+1)

11. Inputs x(t) Outputs z(t) Output Function Present State s(t) Next State s(t+1) State transition Function State Description of Sequential Systems • A sequential system can be specified as a finite state machine (FSM) by specifying • output function: z(t) = H(s(t), x(t)) • state transition function: s(t+1) = G (s(t), x(t))

12. Example 7.3 - Serial Decimal Adder • Inputs: x(t), y(t)  {0,1, …, 9} • Outputs: z(t)  {0, 1, …, 9} • State: c(t)  {0, 1} • Initial State: c(0) = 0 • Functions: • State transition function: c(t+1) = • Output function z(t) = (x(t)+y(t)+c(t)) mod 10 1 if x(t)+y(t)+c(t)  10 0 otherwise

13. PS Inputs x(t) NS, Outputs z(t) State Transition Table • An extended truth table for specifying output function and state transition function in a tabular form

14. PS Inputs x(t) a b Even Even, 1 Odd, 0 Odd Odd, 0 Even, 1 t 0 1 2 3 4 5 6 7 x(t) a b b a b a b a z(t) 1 0 1 1 0 0 1 1 NS, Outputs z(t) Example 7.4: Odd/Even Detector Given a system whose input has two values a and b, and whose output also has two values, 0 and 1. The output at time t is 1 if the number of b’s in the input x(0,t) is even, and 0 otherwise. • Inputs: x(t)  {a,b} • Outputs: z(t)  {0, 1} • State: s(t)  {Even, Odd} • Initial State: s(0) = Even

15. State Diagram • A graphical specification of a sequential system

16. PS Inputs x(t) a b a/1 a/0 b/0 Even Even, 1 Odd, 0 Odd Odd, 0 Even, 1 Even Odd NS, Outputs z(t) b/1 Example: State Diagram

17. logic foroutputs inputs inputs outputs combinational logic for next state combinational logic fornext state logic foroutputs reg reg outputs state feedback state feedback Mealy and Moore Machines • Mealy Machine: • Its output depends upon both input and state • Moore Machine: • Its output depends only upon present state Mealy Machine Moore Machine

18. Example 7.5 - A Moore Machine

19. How to Select State Names • Use integers as state names • Example: A modulo-64 counter • Input: x(t)  {0,1} • Output: z(t)  {0,1,…,63} • State: s(t)  {0,1,…,63} • Initial State: s(0) = 0 • Function: • Transition function: s(t+1) = [s(t)+x(t)] mod 64 • Output function: z(t) = s(t)

20. [si(t)+1] mod 100 if x(t) = i si(t) otherwise i if x(t) = i and si(t) = 99 0 otherwise How to Select State Names (Cont’d) • Use state-vector approach: • state is represented by a vector s = (sn-1, …, s 0) • Example: • A sequential system that counts the occurrence of 55 different events. When the count of event I is a multiple of 100, the output is z(t) = i, otherwise, z(t) = 0 • Input: x(t)  {1, 2, …, 55} • Output: z(t)  {0, 1, 2, …, 55} • State: s(t) = (s55,…,s1), si {0,1,…,99} • State: s(0) = (0,0,…,0) • Functions: • Transition function: si(t+1) = • Output function: z(t) =

21. p if x(t-3,t) = aaba q otherwise 1 if number of 1’s in x(0, t) is even 0 otherwise Case Study 1: Finite Memory Systems • A sequential system has finite memory of length m is z(t) depends only on the last m input values: • z(t) = F(x(t-m+1), t)) • Example 7.12: • z(t) = • Finite memory of length four • All finite-memory machines are FSMs • Not all FSMs are finite-memory • z(t) =

22. 1 if x(t-3,t) = 1101 0 otherwise Case Study 2: Pattern Detector • Detect sub-patterns in the input sequence • Two types: • overlapped and non-overlapped • Example: • Input: x(t)  {0,1} • Output: z(t)  {0,1} • Function: z(t) =

23. Case Study 3: Controller • A FSM that produces control signals as the states are traversed. • Control signals determine actions performed by other parts of the system. • Two types • Autonomous • State transitions follow a fixed sequence of states, independent of any inputs except the clock. • Non-autonomous • The transition is decided by external inputs

24. Vending Machine Controller

25. Vending Machine Controller (Cont’d)

26. State Minimization • Motivation: • High-level design may generate many redundant states • Fewer states may mean fewer state variables • To reduce the complexity and cost • Basic concept: • Two states are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same • (1) Output must be the same in both states • (2) Must transition to equivalent states for all input combinations • Basic Methods: • Table matching • Implication Chart

27. Table Matching Procedure - Overview • Starting with the state table • Step 1: Row matching with respect to outputs • Step 2: Rename the newly partitioned classes • Step 3: List their next state transitions by using new names • Step 4: Check if partitions are same by column matching within classes • If no, go back to Step 1 • If yes, The states are minimal • Write the state table for the minimal states

28. State Minimization - Example 7.14

29. Example 7.14 (Cont’d) • Row Matching: • P1 = (A, C, E) (B, D, F) • Column Matching:

30. 1 2 3 4 P3 (A, C) (E) (B, D) (F) a 1 1 2 4 4 b 3 3 4 3 3 c 3 3 4 1 1 Example 7.14 (Cont’d) • Row Matching: • P2 = (A, C, E) (B, D) (F) • Column Matching: • Row Matching: • P3 = (A, C) (E) (B, D) (F) • Column Matching:

31. Example 7.14 (Cont’d) • Column Matching: • P4 = (A, C) (E) (B, D) (F) = P3 • Stop: The states are minimal

32. Summary • Specification of sequential systems • time-behavior • state-transition table • equation • state diagram • Several common types of sequential systems • pattern detectors • controller • State Minimization

33. Next Lecture • Chapter 8: Sections 8.1-8.7