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SCATS: ( Sixteen Channel Absolute Time Stamper)

SCATS (Sixteen-Channel Absolute Time Stamper) is an electronics system fulfilling stringent time-resolution requirements. The architecture, clock range, dead-time specifications, and performance characteristics are detailed, with emphasis on its simplicity and precision. SCATS utilizes advanced technologies, featuring a data-push architecture, configurable time ranges, and efficient readout mechanisms. The system's functionalities, test board synoptics, and performance evaluation metrics are thoroughly explored.

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SCATS: ( Sixteen Channel Absolute Time Stamper)

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  1. SCATS:(Sixteen Channel Absolute Time Stamper) C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration Meeting – Frascati December 2012

  2. Electronics Requirements Requirements for the TDC: • Step: 200 ps • Time data format over 31 bits covering the trigger latency • Hit time resolution: < 100 ps rms • Count rate capability: 1 MHz/channel with readout dead-time < 2% • Instantaneous dead time: < 50 ns • TMR on state machines and registers • Requirements for the FDIRC electronics chain: • Time resolution ~ 200 ps rms. • Signal measurement • PMT signal: rise time ~ 700 ps • Dynamics ~15 + Dispersion ~3: Input amplitude range from 2mV to 100 mV • Count rate per channel up to 500 kHz (due to background) • Trigger rate up to 150 kHz. • Minimum distance between triggers of about 50 ns. • Dead time < 2%. • Immunity to SEU. The electronics chain: PIF chip Final CAT chip SuperB -Collaboration Meeting – Frascati December 2012

  3. SCATS : a simple architecture The conceptual design is very simple which makes it easy to use: • Data-push architecture • Time range is programmable: (default mode is 2-word) • 1 word => 15 bits => covers 6 µs • 2 words => 31 bits => covers 416 ms • 3 words => 47 bits => covers 7 hr 30 min • 4 words => 53 bits => covers 20 days • SCATS master clock ranges from 100 to 200 MHz (for DLL and counter) • SCATS readout clock is selectable: • internal (½ frequency of the input clock) • external (up to 100 MHz) • SPI bus for slow control • Chip is fully operational at power up. 16-bit data + address and control bits 16-inputs Front-end Part Readout Part Time coding 15 to 53 bits State Machine Clock for front-end SPI bus Slow ctrl Sel TMR Regs Clock for readout SPI SuperB -Collaboration Meeting – Frascati December 2012

  4. Lookinginto SCATS Correcting logics for DLL and Gray counter matching Readout dead time contribution Fine measurement inside a clock period Instantaneous dead time contribution: minimum distance between input hits IEEE NSS Anaheim Nov 2112

  5. SCATS overview Readout FSM • Technology: AMS pureCMOS 0.35µm • Area: 23.4 mm²

  6. SCATS Characterization Test Board synoptics Two types of measurements are required to characterize a TDC: • Fine measurements inside the clock period, performed with external pulser • DLL histogram, DNL , INL and resolution • Measurements linked to the clock synchronous logics and to data readout • Dead time depending on hit rate and readout dataflow capability Test software Scats test board Pulse generator: Agilent HP8110A

  7. Input Dead Time Hit distance = 42.2 ns Hit distance = 42.0 ns The input dead time of the chip is the minimum distance between two consecutive hits which can be detected by SCATS: ~ 43 ns SuperB -Collaboration Meeting – Frascati December 2012

  8. Hit rate acceptance Hit distance = 43.0 ns on channel 3 and 4. Front-end clock = 160 MHz, readout clock = 80 MHz. Some hits are missing The derandomizers get full and hits are missing: this is the readout dead time. The Full-FIFO flag is latched and it is readable by slow control. SuperB -Collaboration Meeting – Frascati December 2012

  9. Hit rate acceptance In order to characterize the hit dead time, we use an individual exponential hit distribution on each channel (centered on 1, 2 or 4 MHz). Digital frames are generated inside the FPGA of the test board. Readout dead time: • One-word mode: @ 4 MHz < 2% • Two-word mode: @ 1 MHz  < 2% @ 2 MHz  < 2 % @ 4 MHz  16 % • Three-word mode: @ 1 MHz  18 % @ 2 MHz 20% • Four-word mode: @ 1 MHz  40 % SuperB -Collaboration Meeting – Frascati December 2012

  10. DLL performances 2 channels are pulsed asynchronously with respect to the DLL clock. • DNL: 12ps rms • DLL step 0 is higher but it can be tuned via internal DAC (still to be done) INL: 40ps rms SuperB -Collaboration Meeting – Frascati December 2012

  11. DLL performances DNL summary for the 16 channels  • All channels are very similar (rms ~ 12ps) INL summary for the 16 channels  • Shape is uniform but INL increases towards the bottom of the chip (rms goes from ~ 30 to ~ 45 ps) • INL pattern is stable and can be corrected by software thanks to a simple addition to hit time The DLL performance is linked to the layout topology. Going from ch0 to ch15, we get closer to the clock receiver and Gray counter which are located at the bottom of the chip.

  12. Time resolution between 2 channels Example of time difference measurement between ch8 & ch10 and ch8 & ch12. Each have different DLLs. Differential resolution is 110-115 ps rms ~ 80 ps rms for single hits. After INL correction, it becomes 88ps rms ~ 63 ps rms for single hits.

  13. Time resolution for single DLL Differential time resolution between two channels that share the same DLL is 70 to 82ps rms after INL correction  50 to 60 ps rmsfor single hits

  14. Bugs to fix in the chip • Counter correction (0/31) in the 2-Word Mode: problem understood and will be corrected. There are two options 1- Increasing the instantenaous dead time by 6.25 ns (only in the 2-word mode). 2- Detecting the error (dedicated flag) and correcting it outside of the chip. • Channel 0 priority : is not a problem at 1MHz but must be understood and corrected. • Data superposition at high rates between ch11 or Ch13 and one of the channels 0, 1 or 2 : this error can be detected and rejected. It seems to happen rarely but this has to be studied more precisely and on different chips. SuperB -Collaboration Meeting – Rome December 2012

  15. The first version of the SCATS TDC is functional. • Single hit resolution is ~ 80 ps rms, ~ 60 ps rms after INL correction • Readout dead time is < 2% in the 2-word mode with 1 MHz exponential input on each channel • DNL is ~ 12 ps rms • INL is < 45 ps rms but can be corrected by software • The next version will: • correct the few bugs and implement TMR on state machines • embed a low walk discriminator, a peak detector and an analog pipeline to associate charge and time. Conclusion SuperB -Collaboration Meeting – Frascati December 2012

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