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XC9500 Series: Advanced Architecture for Predictable Performance

The XC9500 architectural features offer predictable, fast performance with PAL-like architecture, 100% routing capability, flexible function blocks, and powerful macrocell logic. This series supports In-System Programming, bi-directional cascade, and high-speed connections for efficient design implementation.

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XC9500 Series: Advanced Architecture for Predictable Performance

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  1. XC9500 Architectural Features

  2. XC9500 Architectural Features • Predictable, all pins fast, PAL-like architecture • FastCONNECT switch matrix provides 100% routing with very high device utilization • Flexible function block • 36 inputs with 18 outputs • Product term expansion with up to 90 product terms per macrocell • Global and product term clocks • Global and product term output enables • Global and product term set/reset signals

  3. XC9500 Architecture 3 JTAG Controller In-System Programming Controller JTAG Port Function Block 1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Function Block 3 I/O - Global Clocks 3 I/O - Global Set/Reset 1 Function Block n I/O - Global Tri-States 2 or 4

  4. XC9500 Function Block • Flexible “36V18” PAL Blocks

  5. FastCONNECTTM Switch Matrix • 100% routable, high-speed connections

  6. XC9500 Macrocell • Powerful, flexible macrocell logic: • 1 to 90 p-terms • Individual p-term or global signals for clock, OE, set, reset

  7. XC9500 P-Term AllocationExample #1

  8. Complex P-Term AllocationExample #2

  9. XC9500 P-Term Allocator Logic • Flexible, bi-directional cascade / bypass capability

  10. XC9500 Clock, Set/Reset Capability

  11. XC9500 OE Capability

  12. VCCINT 3.8 V (Typ) 0 V Quiescent State No Power No Power Quiescent State User Operation Initialization of User Registers XC9500 Power-Up Characteristics • Well-behaved quiescent characteristics: • JTAG, I/O pins, internal operation disabled • 10 kohm pull-up resistors activated on each user I/O pin

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