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XC9500 CPLDs

XC9500 CPLDs. “ Supporting the Total Product Life Cycle”. Designer's Needs. In-System Programming Enhanced Testability Design changes without PCB changes Mixed 5V/3.3V I/Os High endurance reprogramming Multiple speeds/densities in identical pinouts and packages.

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XC9500 CPLDs

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  1. XC9500 CPLDs “Supporting the Total Product Life Cycle” Technical seminar

  2. Designer's Needs • In-System Programming • Enhanced Testability • Design changes without PCB changes • Mixed 5V/3.3V I/Os • High endurance reprogramming • Multiple speeds/densities in identical pinouts and packages Technical seminar

  3. The Industry’s First 5V Flash CPLD • 5 V In-System Programming (ISP) • High performance • 5ns pin-to-pin speed • 125 MHz count frequency • Large density range • 36 to 288 macrocells (Phase 1 family) • Flexible architecture • optimized for pin-locking • global and product term clock, set/reset, OE • Most complete IEEE 1149.1 (JTAG) • Highest reprogramming endurance • 10,000 program/erase cycles Technical seminar

  4. FastFLASH Cell Typical E2 CPLD Cell 1/3 Area Smaller Cell Size with FastFLASH • Product benefits due to smaller cell • More routing switches in the same area supports pinlocking • Lower parasitic capacitance improves performance • Long term cost improvements due to scalability Technical seminar

  5. XC9500 Architectural Features • Predictable, all pins fast, PAL-like architecture • FastCONNECT switch matrix provides 100% routing with 100% device utilization • Flexible function block • 36 inputs with 18 outputs • product term expansion with up to 90 product terms per macrocell • global and product term clocks • global and product term 3-state enables • global and product term set/reset signals Technical seminar

  6. XC9500 Architecture 3 JTAG Controller In-System Programming Controller JTAG Port Function Block 1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Function Block 3 I/O - Global Clocks 3 I/O - Global Set/Reset 1 Function Block n I/O - Global Tri-States 2 or 4 Technical seminar

  7. 36 FastFLASH Function Block Global Clocks Global 3-State 2 3 I/O Macrocell 1 Product- Term Allocator AND Array From FastCONNECT I/O Macrocell 18 To FastCONNECT Technical seminar

  8. XC9500 Macrocell to/from other macrocells From FastCONNECT SUM-Term Logic 18 XOR Register 36 D/T Q P-Term Allocator P-term Clk R S P-term R&S P-term OE 2 or 4 to/from other macrocells 3 Global Clocks Global R/S Global OEs Technical seminar

  9. XC9500 Advanced Macrocell From Upper Macrocell To Upper Macrocell Global S/R Global CLKs Global S/R Product Term OE From Lower Macrocell To Lower Macrocell Technical seminar

  10. Flexible Cascading Forwards 3 p-terms, retains 2 p-terms • Fast • Bi-directional cascade • collects/delivers available p-terms • Automatically controlled by software • One p-term granularity level Forwards 5 p-terms Macrocell Logic with 18 p-terms Delivers 5 p-terms Delivers 5 p-terms Technical seminar

  11. Macrocell Macrocell Macrocell Feedback Paths • FastCONNECT • Pin • Local FastCONNECT FB X Local feedback FastCONNECT feedback Pin feedback Technical seminar

  12. Global S/R Global 3-State Global Clocks JTAG Complete Interconnectivitywith FastCONNECT™ Function Block Function Block FastCONNECT Function Block Function Block Function Block Function Block Function Block Function Block Technical seminar

  13. 1 2 3 4 36 Restrictive Max7000/S Interconnect Pin Inputs (~ 2 entries / LAB) Macrocells (~2 entries / LAB) Technical seminar

  14. XC9500 FastCONNECT 1 Pin Inputs (~ 3 entries / FB) 2 3 4 36 Macrocells (36 entries / FB) Technical seminar

  15. What is Pin-Locking? • Ability to retain device pin assignments for small to medium design changes • introducing a new variable to existing terms • adding input signals • inverting signals • introducing 1or 2 buried flip flops • adding p-terms • Requires a symmetric, uniform architecture • Requires software focus on pin-locking Technical seminar

  16. Pin-Locking is Key for ISP • Must retain pinouts as the design evolves • best done when the design software initially assigns pins • different from pinout pre-assigning • strong function of utilization in typical CPLD architectures • result of both architecture and software strategy • Pin-locking is valuable • eliminates or reduces PC Board rework • minimizes time to market, saves money • lowers designer frustration, risk Technical seminar

  17. FastCONNECT Function Block I/O Block 36 I/O Block 36 Wired-AND Capability Function Block Leading Edge Features SupportSuperior Pin Locking for ISP 3X more routing switches - superior input/feedback routability Largest block fan-in - 36 direct inputs - wired-AND provides extra logic/more fan-in Powerful bi-directional logic allocation - any number of p-terms (up to 90 max.) Technical seminar

  18. XC9500 Supports Design Changeswith Fixed Pinouts • Design Change XC9500 Feature • Add another input FastCONNECT switch matrix • pin or FB output with 100% connectivity • Add more logic in XC9500 allows expansion • the macrocell up to 90 P-terms • Add additional input 36 total inputs are available • connections to the FB plus FastCONNECT AND gate capability Technical seminar

  19. XC9500 System Features • Enhanced Data Security Features • Read security bits prevent unauthorized reading • Write security bits prevent accidental program/erase • Reduced power option per macrocell • 3.3v/5v outputs • 24 mA, 100% PCI compliant • Output Noise Reduction • Slew rate control • Userprogrammable ground pin capability • Additional Ground Pin • Lower ground inductance • Reduce ground noise Internal Logic User Programmable Ground Pin User I/O Pin User I/O Pin Ground Pin Technical seminar

  20. Advanced System Features • Enhanced Data Security Features • Read security bit prevents unauthorized reading • Write security bit prevents inadvertent user program/erase • System Power Reduction • Reduced power option per macrocell • Output drive capability • 3.3v/5v outputs • 24 mA, 100% PCI compliant outputs • Output Noise Reduction in High-Pincount PQFP Packages • Slew rate control • User programmable ground pins Technical seminar

  21. Planned FastFLASH™ CPLD Family Phase II Expansion 0.6µ Phase I Family XC9536 XC9572 XC95108 XC95144 XC95180 XC95216 XC95288 XC95432 XC95576 Macrocells 36 72 108 144 180 216 288 432 576 Usable Gates 800 1600 2400 3200 4000 4800 6400 9600 12800 tPD (ns) 5 7.5 7.5 7.5 10 10 10 12 15 Registers 36 72 108 144 180 216 288 432 576 Max. User I/Os 34 72 108 133 168 168 192 240 240 44PC 44PQ 84PC 100PQ 84PC 100PQ 160PQ 100PQ 160PQ 208PQ 304PQ 304PQ 304PQ 160PQ 208PQ 160PQ 208PQ Packages Technical seminar

  22. The Next Generation CPLD • The Industry’s first 5V Flash CPLD • Highest program/erase reliability of 10,000 cycles • The best Pin-Locking CPLD architecture • Most complete manufacturing and engineering JTAG support Support for the Total Product Life Cycle Technical seminar

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