ECE 44 8 – FPGA and ASIC Design with VHDL

1. ECE 448 Lab 2 Implementing Combinational and Sequential Logic in VHDL ECE 448 – FPGA and ASIC Design with VHDL George Mason University

2. Agenda for today Part 1: Introduction to Lab 2 Implementing Combinational and Sequential Logic in VHDL Part 2: Testbenches Based on Arrays of Records Part 3: Hands-on Session: Simulation Using Aldec Active-HDL Part 4: Lab Exercise 1 Part 5: Demo of Lab 1

3. Part 1 Introduction to Lab 2 ECE 448 – FPGA and ASIC Design with VHDL

4. Discussion of the Diagram, Requirements, and Hints

5. Task 1: BCD Adder/Subtractor

6. Modes of Operation

7. Examples OP = 0 OP = 1 OP = 2 -63 45 1?? +36 +1 45 182 =-100+82 63 +45 108 63 -45 018

8. Block Diagram: BCD_AS

9. Block Diagram: Nines Complementer

10. Pseudo-Random Number Generators Implemented Using LFSRs

11. Linear Feedback Shift RegisterLFSR • Generates a sequence of numbers that approximates the properties of random numbers • The sequence is fully deterministic, i.e., it can be repeated based on an initial state of LFSR • The period of the sequence may be made very large (typically, 2L-1, where L is an internal state size)

12. Applications of LFSRs • Random Numbers are often important • Testing of VLSI circuits • Cryptography • Monte Carlo simulations • Noise addition • Bit error detection, and many other applications

13. Linear Feedback Shift Register (LFSR) Each stage = D flip-flop  L, C(D)  Length Connection polynomial, C(D) C(D) = 1 + c1D + c2D2 + . . . + cLDL

14. Sj-1 Sj-2 Sj-(L-1) Sj-L Initial state [sL-1, sL-2, . . . , s1, s0] LSFR recursion: sj = c1sj-1 c2sj-2 . . .  cL-1sj-(L-1) cLsj-L for j  L

15. D D D Q Q Q Initializing Serial Shift Register with Parallel Load Load D(3) D(2) D(1) D(0) Sin D Q Clock Enable Q(3) Q(2) Q(1) Q(0) Hint: Use similar technique for initializing LFSR

16. Period of LFSR Period of the Linear Feedback Shift Register  L, C(D)  • If C(D) is irreducible • Period of LFSR is the least positive integer N, such that C(D) | 1 + DN N | 2L - 1 B. If C(D) is primitive N = 2L - 1 LFSR: maximum-length LFSR

18. Multiple Input Signature Register MISR

19. MISR - Multiple Input Signature Register D7 D6 D5 D4 D3 D2 D1 D0 rst rst rst rst rst rst rst rst rst rst rst rst rst rst rst rst D D D D D D D D Q Q Q Q Q Q Q Q en en en en en en en en en Q7 en Q6 en Q5 en Q4 en Q3 en Q2 en Q1 en Q0 AND AND AND AND AND AND AND AND C7 C6 C5 C4 C3 C2 C1 C0 MISR is used to compress multiple inputs D to a single signature Q C=C7..C0 should be declared as a generic in VHDL code For the purpose of testing set C=X”B8”

20. Task 2a: 16-bit LFSR 4 4 4 4 16 LFSR C Q15..12 16 D Q11..8 ld Q7..4 en Clk Q3..0

21. Task 2b: 8-bit MISR 4 4 MISR rst Clk en D7..4 8 Q D3..0 C=C7..C0 should be declared as a generic in VHDL code For the purpose of testing set C=X”B8”

22. Task 3: BCD_AS_TEST 4 4 4 4 4 4 4 4 4 16 LFSR C C CB Q15..12 mod 10 X1 CB 16 D MISR IV Rst Q11..8 X0 mod 10 rst Clk Init BCD_AS en ld Collect 4 Q7..4 Y1 S1 mod 10 D7..4 8 Run Q en Y0 D3..0 S0 mod 10 Clk Q3..0 4 OP Mode

23. Task 4 Tested during the next demo Be prepared to demonstrate the operation of all your testbenches using Aldec Active-HDL and Xilinx ISim

24. Bonus Task 1 Advanced testbench for Part 1 (BCD_AS) based on array of records

25. Bonus Task 2 • Implement the functionality of the entire circuit from Task 3 in C • Calculate the reference output of MISR for every clock cycle after • LFSR is initialized • Run and Collect are simultaneously made active • Allow changing the coefficients of LFSR and MISR using constants

26. Part 2 Testbenches Based on Arrays of Records ECE 448 – FPGA and ASIC Design with VHDL

27. Records ECE 448 – FPGA and ASIC Design with VHDL

28. Records TYPE test_vector IS RECORD operation : STD_LOGIC_VECTOR(1 DOWNTO 0); a : STD_LOGIC; b: STD_LOGIC; y : STD_LOGIC; END RECORD; CONSTANT num_vectors : INTEGER := 16; TYPE test_vectors IS ARRAY (0TOnum_vectors-1) OF test_vector; CONSTANT and_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT or_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT xor_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT xnor_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";

29. Records CONSTANT test_vector_table: test_vectors :=( (operation => AND_OP, a=>'0', b=>'0', y=>'0'), (operation => AND_OP, a=>'0', b=>'1', y=>'0'), (operation => AND_OP, a=>'1', b=>'0', y=>'0'), (operation => AND_OP, a=>'1', b=>'1', y=>'1'), (operation => OR_OP, a=>'0', b=>'0', y=>'0'), (operation => OR_OP, a=>'0', b=>'1', y=>'1'), (operation => OR_OP, a=>'1', b=>'0', y=>'1'), (operation => OR_OP, a=>'1', b=>'1', y=>'1'), (operation => XOR_OP, a=>'0', b=>'0', y=>'0'), (operation => XOR_OP, a=>'0', b=>'1', y=>'1'), (operation => XOR_OP, a=>'1', b=>'0', y=>'1'), (operation => XOR_OP, a=>'1', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'0', b=>'0', y=>'1'), (operation => XNOR_OP, a=>'0', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'0', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'1', y=>'1') );

30. Variables ECE 448 – FPGA and ASIC Design with VHDL

31. Variables - features • Can only be declared within processes and subprograms (functions & procedures) • Initial value can be explicitly specified in the declaration • When assigned take an assigned value immediately • Variable assignments represent the desired behavior, not the structure of the circuit • Can be used freely in testbenches • Should be avoided, or at least used with caution in a synthesizable code

32. Variables - Example testing: PROCESS VARIABLE error_cnt: INTEGER := 0; BEGIN FOR i IN 0 to num_vectors-1 LOOP test_operation <= test_vector_table(i).operation; test_a <= test_vector_table(i).a; test_b <= test_vector_table(i).b; WAIT FOR 10 ns; IF test_y /= test_vector_table(i).y THEN error_cnt := error_cnt + 1; END IF; END LOOP; END PROCESS testing;

33. Using Arrays of Test Vectors in Testbenches ECE 448 – FPGA and ASIC Design with VHDL

34. Testbench (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sevenSegmentTB IS END sevenSegmentTB; ARCHITECTURE testbench OF sevenSegmentTB IS COMPONENTsevenSegment PORT ( bcdInputs : INSTD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUTSTD_LOGIC_VECTOR(6 DOWNTO 0); ); end COMPONENT; CONSTANT PropDelay: time := 40 ns; CONSTANT SimLoopDelay: time := 10 ns;

35. Testbench (2) TYPE vector ISRECORD bcdStimulus: STD_LOGIC_VECTOR(3 DOWNTO 0); sevSegOut: STD_LOGIC_VECTOR(6 DOWNTO 0); END RECORD; CONSTANT NumVectors: INTEGER:= 10; TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector; CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus => "0001", sevSegOut => "1001111"), (bcdStimulus => "0010", sevSegOut => "0010010"), (bcdStimulus => "0011", sevSegOut => "0000110"), (bcdStimulus => "0100", sevSegOut => "1001100"), (bcdStimulus => "0101", sevSegOut => "0100100"), (bcdStimulus => "0110", sevSegOut => "0100000"), (bcdStimulus => "0111", sevSegOut => "0001111"), (bcdStimulus => "1000", sevSegOut => "0000000"), (bcdStimulus => "1001", sevSegOut => "0000100") );

36. Testbench (3) SIGNAL StimInputs: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN u1: sevenSegment PORT MAP ( bcdInputs => StimInputs, seven_seg_outputs => CaptureOutputs);

37. Testbench (4) LoopStim: PROCESS BEGIN FOR i in 0 TO NumVectors-1LOOP StimInputs <= vectorTable(i).bcdStimulus; WAITFOR PropDelay; ASSERT CaptureOutputs == vectorTable(i).sevSegOut REPORT“Incorrect Output” SEVERITYerror; WAIT FOR SimLoopDelay; END LOOP; Verify outputs!

38. Testbench (5) WAIT; END PROCESS; END testbench;

39. Part 3 Hands-on Session: Simulation Using Aldec Active-HDL ECE 448 – FPGA and ASIC Design with VHDL

40. Hands-on Session based on the MLU example with simple testbench

41. Part 4 Lab Exercise 1 ECE 448 – FPGA and ASIC Design with VHDL

42. Interface : ALU

44. ALU: Block Diagram

46. Part 5 Lab 1 Demos ECE 448 – FPGA and ASIC Design with VHDL